Figure 1 depicts a very low level dc current amplifier, including SCF and a small current source., and are the input capacitance, input resistance, and amplification factor of the amplifier having a high input resistance, respectively. As an input signal to the amplifier in our experiment, we utilize a triangular wave voltage produced by the function generator and the differentiating capacitor (reactance attenuator) to obtain a square wave current with a high output impedance. is the output capacitance to the ground of. The input stage of the offset controller is composed of a JFET which has much higher input impedance than the negative feedback circuit has. Its voltage drift is very small (several μV). Therefore, the offset controller does not have much effect on the current detection sensitivity of the amplifier. The SC negative feedback circuit and SCF are shown in Figure 1(b). The former circuit is composed of a basic SC circuit and a feedback rate attenuator. The switches in Figure 1(b) are controlled by two non-overlapping clock signals. The switch is synchronous with and. is synchronous with, and. The switches and in the SCF are synchronous with and, respectively.

From Figure 1(b), the voltage at node, , is given by

and an electric charge at is

From Equation (1) and the relationship that, the electric charge at can be rewritten as

for. The quantity of the charge that is transported from node a to node is equivalent to because

the electric charge at during is totally discharged. Thus, a current, , flowing from node a into node during one clock cycle is

Since the current to be measured in the amplifier flows into the SC circuit,. From the relationship that, the equivalent resistance of SC negative feedback circuit is represented by

while the equivalent SC resistance [7] becomes

where is the clock frequency. The attenuation factor of the attenuator [8] is given by

Thus, from Equations (4) to (6), can be obtained as

It is observed from Equation (6) that x is dependent on the ratio of capacitances of and.

The equivalent SC negative feedback circuit is illustrated in Figure 2(a). It is seen from Equations (5) and (7) that the SC negative feedback circuit is equivalent to the capacitor of and four switches, , , and. The equivalent circuit of the very low level dc current amplifier is shown in Figure 2(b). The box labeled “SC” in Figure 2(b) stands for the SC negative feedback circuit. The figure shows that the equivalent SC negative feedback circuit is connected with the equivalent circuit of the amplifier at the terminals between nodes a and c.

Applying Millman’s theorem to Figure 2(b), the input voltage is represented by

and

where is the angular frequency. The input admittance of the very low level dc current amplifier is

for. Using Equation (8), a simplified input equivalent circuit of the very low level dc current amplifier using SC circuit can be drawn as shown in Figure 2(c).

An enlarged input voltage waveform of the amplifier at the positive final steady-state, , is illustrated with the help of clock waveform in Figure 3. is the clock cycle of the switches., and are, , and a duty ratio of the clock cycle, respectively. Let the input voltage of the amplifier at be. Subscript symbols “+” and “–” indicate just after and just before the time event occurs, respectively. For example, means the voltage just before. The amplitude of the input voltage for a cycle, , is

Since electric charges of the SC circuit are conserved just before and after, the following equation is obtained

The input voltage just before is

From Figure 3 and Equation (10), the voltage is

From Equations (9) and (11), the input voltage just after is given by

The resultant peak voltage during is

Substituting Equation (12) into Equation (13) gives the following equation:

Therefore, the peak output voltage of the amplifier during, , can be written as

It is found from Equation (15) that the theoretical output voltage of the very low level dc current amplifier using SC circuit can be obtained by sampling. In this paper, the SCF is used to sample from the output voltage of the very low level dc current amplifier using SC circuit for the following reasons. Using a sample- and-hold circuit generally requires a clock generator that completely differs from two non-overlapping clock signals utilized by the SC negative feedback circuit. Using a low-pass filter provides for not theoretical output voltage, but approximately half amplitude of output voltage of the amplifier at a final steady-state. On the other hand, using the SCF with the SC circuit allows for sharing the two non-overlapping clock signals. In addition, both the SCF and SC circuit can be manufacturable by the same process. We are easily available to miniaturize SC circuits using IC-compatible techniques. Therefore, the SCF is useful from the viewpoint of miniaturization.

To evaluate response speed of the very low level dc current amplifier, a square wave current with a time period of 5 ms and an amplitude of 10 nA was input to the amplifier. and were set to 1300 and 17 pF, respectively. We fixed the equivalent SC resistance of 1 MΩ using of 10 pF and of 100 kHz. The attenuation factor of 1/100 was also set using both of 1000 pF and of 9.3 pF. The total equivalent resistance of the SC negative feedback circuit was 100 MΩ. The duty ratio of 0.5 was used. A switch model [9] used in the computer simulation is shown in Figure 4. The symbols, , and stand for drain, gate, and source of MOS-FETs. Assuming that parasitic capacitances between two terminals exist, as shown in Figure 4(a) and Figure 4(b), each analog switch composed of a combination of an nMOS and pMOS was used (see Figure 4(c)). Transient analyses of the very low level dc current amplifier using SC circuit were carried out using the electronic circuit simulator PSpice (Cadence Design System, Inc.). Table 1 lists the parasitic capacitance values determined by trial and error.

The amplification factor of the very low level dc current amplifier using SC circuit shown in Figure 1 was set to 62.3 dB. Its output waveform was observed using an oscilloscope. Since the triangular wave voltage, which had a time period of 10 ms and an amplitude of 10 V, was differentiated by the differentiating capacitor of 1.25 pF, a square wave current with a time period of 10 ms and an amplitude of 10 nA was obtained as an input current to the amplifier. As switches for the SC circuit and SCF, we used CMOS analog switches

(MAX326, MAXIM Integrated Products, Inc.) having the maximum leakage current of 10 pA. Further, variable capacitors and were utilized. Parasitic capacitances of analog switches have some effect on equivalent resistance of the SC negative feedback circuit, which causes errors in of the amplifier. Thus, the equivalent SC resistance with the clock frequency of 100 kHz was set to 1 MΩ by adjusting capacitance of, and then the attenuation factor of the attenuator was set to 1/100 by adjusting capacitance of. Referring to Equation (7), the total equivalent resistance of the SC circuit became 100 MΩ. An offset voltage controller, which was connected to the input of the amplifier and had a gain of unity, was also used to cancel the offset voltage in our experiment.

First, based on the assumption that nMOS has exactly the same parasitic capacitances as pMOS has, transient analyses of the amplifier were done. Figure 5 shows the simulation result with the parasitic capacitances shown in Table 1. It can be observed that the output waveforms of the amplifier have vibrations that cause black area due to charge and discharge actions of the SC negative feedback circuit (see Figure 5(a) and Figure 5(b)). Thus, it is difficult to measure an input current from them. Calculating average values of from 10.0 ms to 12.5 ms and from 12.5 ms to 15.0 ms in Figure 5(a), they are respective +1.0 V and –1.0 V. From Equation (15), output voltage of 1 V should be obtained as the theoretical output of the amplifier. The output waveform of the SCF, , is shown in Figure 5(c). In this case, the peaks of the output voltage during were sampled by the SCF. As generally defined, the rise time is the time required for the output waveform to rise from 10% to 90% of its final steady-state value. The rise time of the output waveform of the SCF is 10.3 μs, while that of the am- plifier using conventionally used high-ohmage resistor is 83.8 μs [10] . It is seen from Figure 5(c) that using the

SCF considerably reduces vibrations as well as unnecessary components, and that the input current can be obtained by measuring the amplitude of its output voltage.

Secondly, we also performed computer simulations with an addition of 0.5 pF to each parasitic capacitance of nMOS or pMOS listed in Table 1 to find out which parasitic capacitance would have effect on the output of the amplifier. Table 2 summarizes parasitic capacitances that have effect on offset voltage of the amplifier. For example, all the cases in the switch that, , , and cause generation of offset voltages at the amplifier’s output. On the other hand, parasitic capacitances that are not listed in Table 2 do not have effect on its output voltage. From the simulation results, it is found that differences between value of and that of in, , , , and, and between that of and that of in result in generating offset voltages of the amplifier, and that parasitic capacitive components that are distributed close to the amplifier’s input portion are deeply related to it.

Experimental results are shown in Figure 6. In the experimental result with the duty ratio of, the output amplitude of the amplifier is larger than 1 V. It is also observed that the output waveform at positive and negative final steady-states is rather distorted. On the other hand, in that of, the amplitude becomes smaller than 1 V. It is found from the experimental results that the duty ratio of the clock cycle should be in the range:. Using duty ratios larger than 0.70 leads to output waveform degradation. It is thought that the longer (the shorter) we use, the more stable output waveform can be sampled using the SCF.

Finally, a relationship between the clock frequency and error rate of was investigated. Setting and to respective 100 kHz and 1000 pF, we adjusted both capacitances of and to precisely obtain of 100 MΩ, and then changed ranging from 50 kHz to 200 kHz when, , and, respectively. The equivalent resistance of was obtained by measuring output voltage of the SCF. The relationship between and error rate of, with of 1/100, is shown in Figure 7. Referring to Equation (7), is inversely proportional to. This means that decreasing is equivalent to increasing. It is seen from Figure 7 that there is a tendency for the error rate to decrease as increases. It is thought that the stable output waveform will get longer as increases because of charge action of the SC circuit.

It is found from the simulation results that the parasitic capacitive components that are distributed close to the input portion of the amplifier have effect on the offset voltage. The experimental results show that the duty ratio of the clock cycle has an effective range. The error rate of less than 3.0% in is also obtained in our experiment. These results suggested that the proposed amplifier using SC circuit would provide the measuring device having better properties of both faster response and downsizing.