The basic unit of operation in a quantum system is a qubit, which is similar to a bit in classical computer system. Qubits can represent states 0 and 1, represented by the symbols |0> and |1> respectively. Qubits can also represent an infinite number of state vectors |φ> (called quantum superposition states) between 0 and 1, expressed as:

| φ 〉 = α | 0 〉 + β | 1 〉 (1)

where α and β are complex numbers and satisfy the condition | α | 2 + | β | 2 = 1 .

The operation of the qubit is equivalent to superimposing a unitary matrix U on the state vector of the qubit. The logic gates that operate on qubits in quantum circuits are called quantum gates [12], and each quantum gate can be represented by a 2ⁿ-order unitary matrix, where n represents the number of qubits.

A quantum circuit cascaded by quantum gates is called a quantum circuit. Some specific quantum gates that make up a quantum circuit are called quantum gate libraries [13]. The NCV gate library contains quantum gates such as NOT, CNOT, V, and V⁺ [9]. The Clifford + T gate library includes quantum gates such as NOT, CNOT, H, S, S⁺, T, and T⁺ which is shown in Table 1. The circuit cascaded only by Clifford + T quantum gates is called Clifford + T circuit. The Clifford + T gate libraries are adopted by many quantum physics architectures [14].

The one-dimensional n-qubit circuit has n horizontal lines, respectively representing n quantum bit lines, which are sequentially recorded as l = { l 1 , l 2 , … , l n } from top to bottom. The position of the left to right quantum gate in the line (can be regarded as a vertical line from left to right) indicates the time sequence of the line execution, which is recorded as h = { h 1 , h 2 , … , h m } . Figure 1 is an example of representation of quantum circuit. There l = { 1 , 2 , 3 , 4 } and h = { 1 , 2 , 3 , … , 21 } .

In general, quantum algorithms can be described by reversible circuits of MCT reversible logic gate cascades of multiple (single) control bit(s)/multiple (single) target bit(s). In order to map a reversible circuit to a quantum system for computation, it is necessary to decompose the logic gates in the reversible circuit. It can be seen from the literature [15] and [16] that a two control bits Toffoli gate is decomposed into a circuit composed of NCV gate library quantum gates as shown in Figure 2. AV gate can be decomposed into seven gates as shown in

Figure 3(a). A V⁺ gate can be decomposed into seven gates as shown in Figure 3(b), and the equivalent circuit can be obtained by further simplification as shown in Figure 3(c).

Definition 1: In a one-dimensional quantum circuit, a sequence of quantum gates that can be operated in parallel is called a circuit level. If two or more quantum gates can be combined together in a circuit, their qubits can operate in parallel without disjoint, and these quantum gates are said to form a grouped.

Definition 2: In a one-dimensional circuit, the circuit depth is the number of levels in the circuit.

Definition 3: The T-depth of the Clifford + T circuit is the number of T or T⁺ gates contained on different qubit lines in one level of the circuit.

Definition 4: A “CNOT + T(T⁺) + CNOT” structure is a gate group by the consisting of two CNOT gates and one T or T⁺ gate, called the CTC-structure.

The two control bits and the two target bits of the two CNOT gates are on the same qubit line, and the T (or T⁺) gate is between the two target bits.

Figure 4(a) and Figure 4(b) are represented as CTC (T) and CTC (T⁺) respectively for ease of use. Where line l a is called the control bit line of the CTC-structure, and line l b is called the target bit line of CTC-structure. If the control bit line of the CTC-structure is line i, the target bit line is line j, and the two CNOT gates are located on h 1 and h 2 respectively ( h 1 = h 2 − 2 ), then the CTC-structure can be expressed as C T C h 1 , h 2 ( i , j ) .

Definition 5: The depth of the CTC-structure refers to the number of T (or T⁺) gates that can be operated in parallel in the CTC-structure.

Definition 6: If the depth of the CTC-structure is equal to the number of the circuit input/output qubits, then this CTC-structure is said to be full.

The following properties 1 - 3 [5] can be verified by the matrix representation of the quantum gates, which are multiplied by matrices to obtain the results of their interactions.

Property 1: (a) Two adjacent T-gates are equivalent to a S-gate. Two adjacent T⁺-gates are equivalent to a S⁺-gate.

Property 2: A CNOT gate is equivalent to two consecutive V-gates which have same control bit line and target bit line. A CNOT gate is also equivalent to two consecutive V⁺-gates which have same control bit line and target bit line.

Property 3: 1) Two adjacent CNOT gates with control bits on the same qubit line and target bits on the same qubit line can cancel each other out. 2) Two adjacent H-gates can cancel each other out. 3) Two adjacent T and T⁺-gates can cancel each other out. 4) Two adjacent S and S⁺-gates can cancel each other out.

Property 4: The combinations of two adjacent 2-qubit gates are equivalent, if the control bits are on the same qubit line, and their combinations are switched [5]. Analogously, the combinations of two adjacent 2-qubit gates are equivalent,

if the target bits are on the same qubit line, and their combinations are switched.

Property 5: If the T-gate (or T⁺-gate) and the 2-qubit gate control bit are on the same qubit line and adjacent to each other, then the combination of the T-gate (or T⁺-gate) and the 2-qubit gate on the left and right sides of the control bit of the 2-qubit gate are equivalent [5].

Property 6 [5]: For two CTC(T) structures, if the control line of a CTC(T) structure is the target line of the other CTC(T) structure, then the two CTC(T) structures are equivalent. Analogously, For two CTC(T⁺) structures, if the control line of a CTC(T⁺) structure is the target line of the other CTC(T⁺) structure, then the two CTC(T⁺) structures are equivalent.

Property 7 [5]: The combination of the 2-qubit gate and the CTC(T) structure are equivalent for the right and the left of CTC(T) structure, if the control bit of the 2-qubit gate is on the target bit line of the CTC(T) structure and the target bit of the 2-qubit gate is not on the line crossed by CTC(T). The combination of the 2-qubit gate and the CTC(T⁺) structure are equivalent for the right and the left of CTC(T⁺) structure, if the control bit of the 2-qubit gate is on the target bit line of the CTC(T⁺) structure and the target bit of the 2-qubit gate are not on the line crossed by CTC(T⁺).

Property 8: The subcircuit of the CNOT gate combination is equivalent as shown in Figures 5(a)-(c).

The equivalence of the above subcircuits can be easily verified by the truth table.

Conclusion 1: The combination of two adjacent T-gates and 2-qubit gate are equivalent on the right and the left of control bit of this 2-qubit gate.

The combination of two adjacent T⁺-gates and 2-qubit gate are equivalent on the right and the left of control bit of 2-qubit gate.

The above inferences are readily available based on property 5.

Generally, the arbitrary combination of m (m ≥ 1) 2-qubit gates and n (n ≥ 1) T-gates (or T⁺-gates) are equivalent, if the control bits of m (m ≥ 1) 2-qubit gates and n (n ≥ 1) T-gates (or T⁺-gates) are on the same qubit line.

Conclusion 2: According to property 1, the S-gate (or S⁺-gate) distributed on the left and right sides of the control bit is equivalent for a combination of an S-gate (or S⁺-gate) on the control bit line of a two-qubit gate and the two-qubit gate. It can be seen from the conclusion 1.

Conclusion 3: The combination of single quantum gate (T, T⁺, S, S⁺) located on the left and right side of CTC structure is equivalent if the single quantum gate is on the same quantum bit line of CTC-structure.

Theorem 1: 1) Any combinations of the CTC-structure with the T-gates on

its control bit line and target bit line are equivalent. 2) Any combinations of the CTC-structure with the T⁺-gates on its control bit line and target bit line are equivalent.

Proof: As long as proof 1), then 2) is available as the same.

1) According to the Property 6, the CTC-structure interchange control bit line with target bit line is equivalent, so the combination of a T gate and a CTC-structure on the same qubit line is also equivalent. As show in Figure 6 that Figure 6(a) is equivalent to Figure 6(b);

2) According to the Property 5, the T gate of Figure 6(b) can be moved to the right side of the first CNOT gate. Similarly, it can be moved to the right side of the second CNOT gate to get Figure 6(c). As show in Figure 6 that Figure 6(b) is equivalent to Figure 6(c);

3) According to the Property 6, the CTC-structure interchange control bit line with target bit line is equivalent, therefore, the combination of the CTC-structure and the T gate on the same bit line is also equivalent. As show in Figure 6 that Figure 6(c) and Figure 6(d) are equivalent.

QED ■

Corollary 1: The combination of S-gate (or S⁺-gate) and CTC-structure is equivalent when S-gate (or S⁺-gate) is on the left or right sides of the target position of the CTC-structure according to property 1 and theorem 1.

Theorem 2: In an 1-dimensional quantum circuit, let V ′ = { V , V + } , if there are consecutive mV-gates and nV⁺-gates, the control bit line of V' and the target bit line of V' are same respectively, then the target bit line of the m + nV'-gates can decompose into sub-circuit structure and the number of quantum gates are:

{ H + Σ + H ,     | m − n |   i s   e v e n H + Σ + T ′ + H ,     | m − n |   i s   o d d (2)

the control bit line of this m + nV'-gates can decompose into sub-circuit structure and the number of quantum gates are:

{ Σ ,     | m − n |   i s   e v e n 　 Σ + T ′ ,     | m − n |   i s   o d d (3)

where T ′ = { T , T + } , S ′ = { S , S + } , Σ = m ∗ CTC ( T + ) + n ∗ CTC ( T ) + ⌊ | m − n | 2 ⌋ ∗ S ′ .

Proof: In an 1-dimensional quantum circuit, it is assumed that there are k quantum bit lines l (i.e. the input/output of the quantum line is k), that is, L 1 = { l 1 , l 2 , … , l k } . If there are consecutive m target bits of V-gates and n target bits of -gates on the i-th quantum bit line, i ∈ { 1 , 2 , … , k } . Let V ′ = { V , V + } =   < V ′ 1 , V ′ 2 , … , V ′ m , V ′ m + 1 , … , V ′ m + n > , then:

The target bit line of V-gate in V ′ can be decomposed into:

H + CTC ( T + ) + T + H (4)

The target bit line of V⁺-gate in V ′ can be decomposed into:

H + CTC ( T ) + T + + H (5)

It can be seen that when m, n ≥ 1, continuous m + n V'-gates are decomposed, and m + n − 1 pair of H-gates are adjacent on the target bit line of CTC-structure. In (1) and (2), the first H-gate and the last H-gate are the remaining, and there are m + n CTC-structures and m T-gates and nT⁺-gates between this two H-gates. By the theorem 1, these mT-gates and nT⁺-gates can be moved so that they are adjacent. So there have:

1) When m>n, there are n T-gates and nT⁺-gates are eliminated and ⌊(m − n)/2⌋ pairs of T-gates are replaced by ⌊(m − n)/2⌋ S-gates. If m-n is an even number, all T gates are replaced; if m-n is an odd number, then remain a T-gate. The target bit line of V ′ -gate can eventually be decomposed into:

{ H + m ∗ CTC ( T + ) + n ∗ CTC ( T ) + ⌊ m − n 2 ⌋ ∗ S + H ,     m − n   i s   e v e n H + m ∗ CTC ( T + ) + n ∗ CTC ( T ) + ⌊ m − n 2 ⌋ ∗ S + T + H ,     m − n   i s   o d d (6)

2) When m = n, all T-gates and T⁺-gates are eliminated. The target bit line of V ′ -gate can eventually be decomposed into:

H + m ∗ CTC ( T + ) + n ∗ CTC ( T ) + H (7)

3) When m < n, there are m T-gates and m T⁺-gates are eliminated, and ⌊ ( n − m ) / 2 ⌋ pairs of T⁺-gates are replaced by ⌊ ( n − m ) / 2 ⌋ S⁺-gates. If n-m is an even number, all T⁺-gates are replaced and if n-m is an odd number then remaining a T⁺-gate. The target bit line of the V ′ -gate can be eventually decomposed into:

{ H + m ∗ CTC ( T + ) + n ∗ CTC ( T ) + ⌊ n − m 2 ⌋ ∗ S + + H ,     n − m   i s   e v e n H + m ∗ CTC ( T + ) + n ∗ CTC ( T ) + ⌊ n − m 2 ⌋ ∗ S + + T + + H ,     n − m   i s   o d d (8)

The control bit of V-gate and V⁺-gate in V ′ can be decomposed into the form of CTC ( T + ) + T and CTC ( T ) + T + respectively at the control bit line.

The control bit of mV-gates and nV⁺-gates in V ′ may be distributed on the L 2 = { l 1 , … , l i − 1 , l i + 1 , … , l k } . When m, n ≥ 1, after successive m + nV' gates are decomposed, there are a total of m + n CTC-structures, mT-gates and nT⁺-gates on all control bit lines. Among them, the l j ( l j ∈ L 2 ) qubit line has m j T -gates, n j T + -gates and m j + n j CTC-structures, where m = ∑ j = 1 k m j , n = ∑ j = 1 k n j , j ≠ i .

By theorem 1, these m j T -gates and n j T + -gates can be moved to be adjacent, so:

1) When m j > n j , there are n j T -gates and n j T + -gates are eliminated; ⌊ ( m j − n j ) / 2 ⌋ pairs of T-gates are replaced by ⌊ ( m j − n j ) / 2 ⌋ S-gates. If m j − n j is an even number, all T-gates are replaced, and if m j − n j is an odd number, then remain a T-gate. The control bit line of the V ′ -gate can be finally decomposed into:

{ m j ∗ CTC ( T + ) + n j ∗ CTC ( T ) + ⌊ m j − n j 2 ⌋ ∗ S ,     m j − n j   i s   e v e n m j ∗ CTC ( T + ) + n j ∗ CTC ( T ) + ⌊ m j − n j 2 ⌋ ∗ S + T ,     m j − n j   i s   o d d (9)

2) When m j = n j , all m j T -gates and m j T + -gates are eliminated. The control bit line of V ′ -gate can be finally decomposed into:

m j ∗ CTC ( T + ) + n j ∗ CTC ( T ) (10)

3) When m j < n j , m j T gates and m j T + -gates are eliminated, and ⌊ ( n j − m j ) / 2 ⌋ pairs of T⁺-gates are replaced by ⌊ ( n j − m j ) / 2 ⌋ S⁺-gates. If n j − m j is an even number, all T⁺-gates are replaced and if n j − m j is an odd number, then remain a T⁺-gate. The control bit line of the V ′ -gate can be finally decomposed into:

{ m j ∗ CTC ( T + ) + n j ∗ CTC ( T ) + ⌊ n j − m j 2 ⌋ ∗ S + ,     n − m   i s   e v e n m j ∗ CTC ( T + ) + n j ∗ CTC ( T ) + ⌊ n j − m j 2 ⌋ ∗ S + + T + ,     n − m   i s   o d d (11)

QED■

As shown in Figure 7(a), the circuit has eight 2-qubit gates (G₁ to G₈ from left to right), where G₁, G₃, G₅, G₈ are V ′ ( V ′ ∈ { V , V + } ) gates whose target bits are

on the same qubit line l c . The circuit after decomposition is shown in Figure 7(b) where the second H gate and T c gate generated by G₁ are eliminated respectively with the first H gate and T c + gate generated by G₃, the second H gate and T c + gate generated by G₃ are eliminated respectively with the first H gate and T c gate generated by G₅, while the H gate generated by G₈ cannot cancel out with the H gate generated by G₅ because of the blocking of the G₆ target bit. The T a generated by G₅ and G₈ respectively can be merged into S a .

In order to obtain the quantum circuit composed of Clifford + T gate, using the equivalent circuit given in Figure 3 and the related theory of theorem 2 to decompose NCV circuit.

The circuit is initially optimized with the relevant properties in the decomposition process. The decomposition algorithm is shown in Algorithm 1.

In order to deepen the depth of the CTC-structure, reduce the depth of the circuit, improve the parallelism of the circuit, the decomposed Clifford + T circuit need to be structured and the main goal is to make the depth of each CTC-structure equal to the number of qubits (That is to say, make the CTC-structure to be fully occupied). The CTC-structure depth deepening algorithm is shown in Algorithm 2.

After deepening the depth of the CTC-structure of the circuit, there will be many adjacent CNOT gates. The optimization of continuous CNOT gates can reduce the number of gates. Algorithm 3 is CNOT optimization algorithm.

In some practical quantum techniques, quantum bit interactions of quantum

Algorithm 1. NCV decomposition algorithm.

Algorithm 2. CTC-structure depth deepening algorithm.

Algorithm 3. CNOT optimization algorithm.

gates are required to satisfy linear nearest neighbor constraints. In a quantum logic circuit, to exchange the logic values of certain two circuits, it can generally be realized by inserting a SWAP-gate. The SWAP-gate also needs to satisfy the linear nearest neighbor in the nearest neighbor constrained quantum circuit, it is called the nearest neighbor SWAP gate (NNS gate) [7]. An NNS gate is equivalent to three cascades of CNOT gates that satisfy the linear nearest neighbor architecture, as shown in Figure 8(a). Some quantum circuit physical structures require even stronger constraints. For example, IBM QX [17] [18] requires that the CONT gates in different directions be flipped through the H gate to be in the same direction (control bits and target bits are on two qubits), as shown in Figure 8(b). Converting a non-LNN Clifford + T circuit into an LNN Clifford + T circuit is usually done by inserting several NNS gates, as shown in Figure 9. Figure 9(a) is a non-LNN circuit, Figure 9(b) is equivalent LNN circuit by insert SWAP gates, Figure 9(c) is equivalent form of NNS gate.

It can be seen from the literature [1] that the linear nearest neighbor cost of the 2-qubit gate G in a quantum circuit is:

G n n c = | l C − l T | − 1 (12)

where l C and l T are the number of the control bit line and the target bit line of G, respectively, the nearest neighbor cost of a Clifford + T circuit is:

C C ′ = ∑ i = 1 K     G n n c × N − i + 1 N , ( 1 < K ≤ N ) (13)

where N is the number of quantum gates in the Clifford + T circuit and K is the linear nearest neighbor cost calculation coefficient of the circuit.

This paper presents an adaptive Clifford + T circuit neighborhood optimization algorithm, such as Algorithm 4. The optimized Clifford + T circuit is scanned from left to right, and all LNN schemes are listed for the first non-LNN 2-qubit gate is encountered. Calculate the C C ′ of the remaining circuit after each scheme is executed, select the scheme with the smallest C C ′ , insert the NNS gates into the circuit one after the other, then continue to scan the remaining circuits, and iteratively execute the above steps until all the quantum gates reached LNN. The algorithm is executed for all coefficients K, and the scheme with the least number of inserted switching gates is recorded for output.

The time complexity of the algorithm is O ( L × N × K ) , where L is the quantum number. For small-scale circuits, try all the coefficients K to find the optimal solution. For large-scale circuits, K can be reduced to a constant term in order to reduce algorithm runtime.