<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE article  PUBLIC "-//NLM//DTD Journal Publishing DTD v3.0 20080202//EN" "http://dtd.nlm.nih.gov/publishing/3.0/journalpublishing3.dtd"><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" dtd-version="3.0" xml:lang="en" article-type="research article"><front><journal-meta><journal-id journal-id-type="publisher-id">CS</journal-id><journal-title-group><journal-title>Circuits and Systems</journal-title></journal-title-group><issn pub-type="epub">2153-1285</issn><publisher><publisher-name>Scientific Research Publishing</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.4236/cs.2017.81002</article-id><article-id pub-id-type="publisher-id">CS-73816</article-id><article-categories><subj-group subj-group-type="heading"><subject>Articles</subject></subj-group><subj-group subj-group-type="Discipline-v2"><subject>Computer Science&amp;Communications</subject><subject> Engineering</subject><subject> Physics&amp;Mathematics</subject></subj-group></article-categories><title-group><article-title>
 
 
  CMOS VDIBAs-Based Single-Resistance-Controlled Voltage-Mode Sinusoidal Oscillator
 
</article-title></title-group><contrib-group><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Kanhaiya</surname><given-names>Lal Pushkar</given-names></name><xref ref-type="aff" rid="aff1"><sup>1</sup></xref><xref ref-type="corresp" rid="cor1"><sup>*</sup></xref></contrib><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Ghanshyam</surname><given-names>Singh</given-names></name><xref ref-type="aff" rid="aff2"><sup>2</sup></xref></contrib><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Rajendra</surname><given-names>Kumar Goel</given-names></name><xref ref-type="aff" rid="aff1"><sup>1</sup></xref></contrib></contrib-group><aff id="aff2"><addr-line>Department of Electronics and Communication Engineering, HMR Institute of Technology and Management (HMRIT), Delhi, India</addr-line></aff><aff id="aff1"><addr-line>Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, New Delhi, India</addr-line></aff><author-notes><corresp id="cor1">* E-mail:<email>klpushkar17@gmail.com(KLP)</email>;</corresp></author-notes><pub-date pub-type="epub"><day>10</day><month>01</month><year>2017</year></pub-date><volume>08</volume><issue>01</issue><fpage>14</fpage><lpage>22</lpage><history><date date-type="received"><day>19,</day>	<month>December</month>	<year>2016</year></date><date date-type="rev-recd"><day>22,</day>	<month>January</month>	<year>2017</year>	</date><date date-type="accepted"><day>25,</day>	<month>January</month>	<year>2017</year></date></history><permissions><copyright-statement>&#169; Copyright  2014 by authors and Scientific Research Publishing Inc. </copyright-statement><copyright-year>2014</copyright-year><license><license-p>This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/</license-p></license></permissions><abstract><p>
 
 
  In this communication, a new single-resistance controlled sinusoidal oscillator (SRCO) has been presented. The presented SRCO uses two voltage differencing inverting buffered amplifiers (VDIBAs), one resistor and two capacitors in which one is grounded (GC) and the other one is floating (FC). The proposed structure offers the following advantageous features: 1) independent control of oscillation condition (OC) and oscillation frequency (OF); 2) low passive and active sensitivities and 3) very good frequency stability. The non-ideal effects of the VDIBA on the proposed oscillator have also been investigated. The proposed SRCO has been tested for its robustness using Monte-Carlo simulations. The check of the validity of the presented SRCO has been established by SPICE simulations using 0.18 μm TSMC technology.
 
</p></abstract><kwd-group><kwd>Sinusoidal Oscillator</kwd><kwd> Voltage Differencing Inverting Buffered Amplifier</kwd><kwd> Voltage-Mode Circuits</kwd><kwd> Analog Circuit Design</kwd></kwd-group></article-meta></front><body><sec id="s1"><title>1. Introduction</title><p>In analog signal processing and circuit design, realization of active filters and oscillators has become the important research areas. In reference [<xref ref-type="bibr" rid="scirp.73816-ref1">1</xref>] Biolek, Senani, Biolkova, and Kolka have introduced a number of modern analog active building blocks and VDIBA is one of them which is emerging very flexible and versatile active building block for analog signal processing and signal generation. The role played by SRCOs in control systems, signal processing, instrumentation and measurement and communication systems is well established in the open literature (see [<xref ref-type="bibr" rid="scirp.73816-ref2">2</xref>] [<xref ref-type="bibr" rid="scirp.73816-ref3">3</xref>] [<xref ref-type="bibr" rid="scirp.73816-ref4">4</xref>] and the references cited therein). Considerable attention has been given by the various researchers in the realization of SRCOs using various active building blocks because of their several merits over conventional op-amp-based SRCOs (see [<xref ref-type="bibr" rid="scirp.73816-ref5">5</xref>] - [<xref ref-type="bibr" rid="scirp.73816-ref16">16</xref>] and the references cited therein). The applications, advantages and usefulness of VDIBA have now been recognized in the realization of the first-order all-pass filter and oscillator [<xref ref-type="bibr" rid="scirp.73816-ref17">17</xref>] [<xref ref-type="bibr" rid="scirp.73816-ref18">18</xref>] , and universal biquadratic filters [<xref ref-type="bibr" rid="scirp.73816-ref19">19</xref>] [<xref ref-type="bibr" rid="scirp.73816-ref20">20</xref>] . However, to the best knowledge and belief of the authors, none of the SRCOs using VDIBAs has yet been presented in the literature with independent control of oscillation condition (OC) and oscillation frequency (OF) so far. Therefore, the purpose of this communication is to present a new SRCO using two VDIBAs along with a bare minimum number of three passive components. The proposed structure offers: 1) independent electronic control of oscillation condition; 2) independent control of oscillation frequency through a resistor; 3) low passive and active sensitivities and 4) very good frequency stability. The workability of the proposed SRCO has been confirmed by SPICE simulations using 0.18 &#181;m TSMC technology.</p></sec><sec id="s2"><title>2. New Oscillator Circuit</title><p>The symbolic notation and equivalent model of the VDIBA are given in <xref ref-type="fig" rid="fig1">Figure 1</xref>(a) and <xref ref-type="fig" rid="fig1">Figure 1</xref>(b) respectively [<xref ref-type="bibr" rid="scirp.73816-ref17">17</xref>] . The structure of VDIBA has two voltage inputs of high impedance, a voltage input terminal of low impedance and a current output terminal of high impedance. The ideal terminal equations between port voltages and currents can be expressed as: I<sub>+</sub> = 0 = I<sub>−</sub>, I<sub>z</sub> = g<sub>m</sub> (V<sub>+</sub> − V<sub>−</sub>) and V<sub>w</sub><sub>−</sub> = −V<sub>z</sub>, where g<sub>m</sub>, represents the transconductance of VDIBA.</p><p>The presented single-resistance-controlled sinusoidal oscillator circuit is shown in <xref ref-type="fig" rid="fig2">Figure 2</xref>.</p><p>The characteristic equation (CE) of the proposed SRCO of <xref ref-type="fig" rid="fig2">Figure 2</xref>, using a routine circuit analysis can easily be obtained as:</p><p>CE:</p><p>s 2 C 1 C 2 + s { C 1 g m 2 − C 2 g m 1 } + g m 2 R 0 = 0 (1)</p><p>From Equation (1), the oscillation condition (OC) and oscillation frequency (OF) can be determined as:</p><p>OC:</p><p>{ C 1 g m 2 − C 2 g m 1 } ≤ 0 (2)</p><p>and</p><p>OF:</p><p>ω 0 = g m 2 C 1 C 2 R 0 (3)</p><p>From Equations (2) and (3), it is obvious that OF is independently controllable by resistor R<sub>0</sub> and OC is independently controllable electronically by transconductance g<sub>m</sub><sub>1</sub>.</p></sec><sec id="s3"><title>3. Frequency Stability Analysis of the Presented SRCO</title><p>Frequency stability may be considered to be an important figure of merit of an oscillator. The frequency stability factor is defined as S F = d φ ( u ) / d u [<xref ref-type="bibr" rid="scirp.73816-ref4">4</xref>] , where u = ω / ω 0 is the normalized frequency, and φ ( u ) represents the phase function of the open loop transfer function of the oscillator circuit, with C<sub>1</sub> = C/2, C<sub>2 </sub>= C, R<sub>0 </sub>= R/n and g<sub>m</sub><sub>1</sub> = g<sub>m</sub><sub>2</sub> = 1/R, S<sup>F</sup> for the proposed SRCO is found to be</p><p>S F = 2 2 n (4)</p><p>Thus for larger values of n, the presented oscillator circuit enjoys a very good frequency stability.</p></sec><sec id="s4"><title>4. Non-Ideal Analysis and Sensitivity Performance</title><p>Let R Z and C Z denote the parasitic resistance and parasitic capacitance of the Z-terminal of VDIBA. Taking the non-idealities into account, namely, the voltage of W-terminal V W − = ( − β + V Z ) where β + = 1 − ε p ( ε p &lt; &lt; 1 ) denotes the voltage tracking error of Z-terminal of VDIBA, the expressions for characteristic equation, CO and FO respectively become:</p><p>s 2 { C 1 C 2 + ( C 1 + C 2 + C z ) C z } + s { ( C 1 + C z ) ( 1 R z + β + g m 2 ) + ( C 2 + C z ) ( 1 R 0 + 1 R z ) − β + 2 C 2 ( g m 1 + 1 R 0 ) } + ( 1 R 0 + 1 R z ) ( 1 R z + β + g m 2 ) = 0                           (5)</p><p>Therefore the expressions for OC and OF are given as:</p><p>OC:</p><p>{ ( C 1 + C z ) ( 1 + β + g m 2 R z ) R 0 + ( C 2 + C z ) ( R 0 + R z ) − β + 2 R z C 2 ( 1 + g m 1 R 0 ) } ≤ 0 (6)</p><p>OF:</p><p>ω 0 = R 0 + R z + β + g m 2 R z ( R 0 + R z ) R 0 R z 2 { C z ( C 1 + C 2 + C z ) + C 1 C 2 } (7)</p><p>Therefore the active and passive sensitivities can be obtained as:</p><p>S C 1 ω 0 = − 1 2 1 1 + C z 2 + C 2 C Z C 1 ( C 2 + C Z ) , S C 2 ω 0 = − 1 2 1 1 + C z 2 + C 1 C Z C 2 ( C 1 + C Z ) , S R 0 ω 0 = − 1 2 { R z R 0 + R z } (8)</p><p>S C Z ω 0 = − 1 2 1 1 + C 1 C 2 − C z 2 C z ( C 1 + C 2 + 2 C Z ) , S R z ω 0 = − 1 2 { 2 R 0 + R z ( 1 + β + g m 2 R 0 ) R 0 + R z + β + g m 2 R z ( R 0 + R z ) } (9)</p><p>S β + ω 0 = 1 2 1 1 + 1 β + g m 2 R z = S g m 2 ω 0 (10)</p><p>Ideally, the various sensitivities of OF with respect to passive elements C<sub>z</sub>, R<sub>z</sub>, C<sub>1</sub>, and C<sub>2</sub> are found to be</p><p>S C z ω 0 = S R z ω 0 = 0 , S C 1 ω 0 = S C 2 ω 0 = − 1 2 (11)</p><p>For the typical values of C<sub>z</sub> = 0.81 pF, R<sub>z</sub><sub> </sub>= 53 kΩ, β<sup>+</sup> = 1 along with C<sub>1</sub> = 0.5 nF, C<sub>2</sub> = 1.0 nF, R<sub>0</sub> = 950 Ω, the various sensitivities are found to be S C 1 ω 0 = − 0.391 , S C 2 ω 0 = − 0.276 , S C Z ω 0 = − 0.533 , S R 0 ω 0 = − 0.491 , S β + ω 0 = 0.477 = S g m ω 0 ,</p><p>S R Z ω 0 = − 0.0241 which are all low.</p><p><xref ref-type="fig" rid="fig3">Figure 3</xref> shows the CMOS implementation of the VDIBA used, which was biased with V<sub>DD</sub> = 0.9 V D.C. = −V<sub>SS</sub> and I<sub>b</sub> was taken 100 &#181;A.</p></sec><sec id="s5"><title>5. Simulation Results</title><p>To confirm theoretical analysis, the proposed SRCO was simulated using CMOS VDIBA (as shown in <xref ref-type="fig" rid="fig3">Figure 3</xref>). The passive components were used as C<sub>1</sub> = 0.5 nF, C<sub>2</sub> =1.0 nF, R<sub>0</sub> = 950 Ω. The transconductance of VDIBA was controlled by bias current I<sub>b</sub>. SPICE generated output waveforms indicating transient and steady state responses are shown in <xref ref-type="fig" rid="fig4">Figure 4</xref>(a) and <xref ref-type="fig" rid="fig4">Figure 4</xref>(b) respectively.</p><p>These results, thus, confirm the validity of the proposed configuration. <xref ref-type="fig" rid="fig5">Figure 5</xref> shows the output spectrum, where the total harmonic distortion (THD) is found to be 1.996%. <xref ref-type="fig" rid="fig6">Figure 6</xref> shows the variation of frequency with resistance R<sub>0</sub>. A comparison with other previously known SRCOs using different active building blocks has been given in <xref ref-type="table" rid="table1">Table 1</xref>.</p><p>The implementation of CMOS VDIBA employing 0.18 μm TSMC technology was used from [<xref ref-type="bibr" rid="scirp.73816-ref17">17</xref>] and the device parameters were taken from [<xref ref-type="bibr" rid="scirp.73816-ref21">21</xref>] . The aspect ratios of various MOSFETs used in CMOS VDIBA of <xref ref-type="fig" rid="fig7">Figure 7</xref> were taken from reference [<xref ref-type="bibr" rid="scirp.73816-ref18">18</xref>] .</p><p>From Equations (8) - (10), this is obvious that the values of various sensitivities of passive and active components are less than half.</p></sec><sec id="s6"><title>6. Conclusion</title><p>This work presents VDIBAs-based SRCO which employs minimum number of passive elements (namely, one resistor, two capacitors) and offers independent control of OF through the resistor R<sub>0</sub> and OC through the transconductance g<sub>m</sub><sub>1</sub> (thus the circuit enjoys the electronic control of OC), low passive and active sen-</p><table-wrap id="table1" ><label><xref ref-type="table" rid="table1">Table 1</xref></label><caption><title> A comparison with other previously known SRCOs using different active build- ing blocks</title></caption><table><tbody><thead><tr><th align="center" valign="middle" >Reference</th><th align="center" valign="middle" >Active Element</th><th align="center" valign="middle" >Number of Active Element(s)</th><th align="center" valign="middle" >Number of GC</th><th align="center" valign="middle" >Number of FC</th><th align="center" valign="middle" >Number. of Resistors</th><th align="center" valign="middle" >Whether OC and OF are Independently Controllable?</th></tr></thead><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref5">5</xref>]</td><td align="center" valign="middle" >CFOA</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >3</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref6">6</xref>]</td><td align="center" valign="middle" >CC-II (+)</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >3</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref7">7</xref>]</td><td align="center" valign="middle" >CC-II (−) + Buffer</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >0</td><td align="center" valign="middle" >3</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref8">8</xref>]</td><td align="center" valign="middle" >PFTFN</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >3</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref9">9</xref>]</td><td align="center" valign="middle" >PNFTN</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >0</td><td align="center" valign="middle" >4</td><td align="center" valign="middle" >NO</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref10">10</xref>]</td><td align="center" valign="middle" >NFTFN + Buffer</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >0</td><td align="center" valign="middle" >3</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref11">11</xref>]</td><td align="center" valign="middle" >DVCCC</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >0</td><td align="center" valign="middle" >3</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref12">12</xref>]</td><td align="center" valign="middle" >DVCCC</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >0</td><td align="center" valign="middle" >3/2</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref13">13</xref>]</td><td align="center" valign="middle" >CDBA</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1 virtually grounded)</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >3</td><td align="center" valign="middle" >YES( only in second topology of <xref ref-type="table" rid="table1">Table 1</xref>)</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref14">14</xref>]</td><td align="center" valign="middle" >OTRA</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1 virtually grounded)</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >3</td><td align="center" valign="middle" >NO</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref15">15</xref>]</td><td align="center" valign="middle" >CDTA</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref16">16</xref>]</td><td align="center" valign="middle" >VD-DIBA</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >0</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref17">17</xref>]</td><td align="center" valign="middle" >VDIBA</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >NO</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref22">22</xref>]</td><td align="center" valign="middle" >VD-DIBA</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >0</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >[<xref ref-type="bibr" rid="scirp.73816-ref23">23</xref>]</td><td align="center" valign="middle" >VD-DIBA</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >YES</td></tr><tr><td align="center" valign="middle" >Proposed</td><td align="center" valign="middle" >VDIBA</td><td align="center" valign="middle" >2</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >1</td><td align="center" valign="middle" >YES</td></tr></tbody></table></table-wrap><p>sitivities and a very good frequency stability. This communication, therefore, added a new application circuit to the existing repertoire of VDIBAs-based application circuits.</p></sec><sec id="s7"><title>Acknowledgements</title><p>The authors gratefully acknowledge Prof. Dr. D. R. Bhaskar, Professor, Department of Electronics and Communication Engineering, Delhi Technological University, Shahbad Daulatpur, Main Bawana Road, Delhi-110042, India, useful suggestions/discussions.</p></sec><sec id="s8"><title>Cite this paper</title><p>Pushkar, K.L., Singh, G. and Goel,<sup> </sup>R.K. (2017) CMOS VDIBAs-Based Single-Resistance-Controll- ed Voltage-Mode Sinusoidal Oscillator. Circuits and Systems, 8, 14-22. http://dx.doi.org/10.4236/cs.2017.81002</p></sec></body><back><ref-list><title>References</title><ref id="scirp.73816-ref1"><label>1</label><mixed-citation publication-type="other" xlink:type="simple">Biolek, D., Senani, R., Biolkova, V. and Kolka, Z. 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