Single diode model is the simplest as it has a current source in parallel to a diode. This

model is upgraded by the inclusion of one series resistance, R_s [21] [22] . In spite of its simplicity; it exhibits acute deficiencies when suffered from temperature deviations. An accretion of the model which introduces a supplementary shunt resistance R_p [23] [24] is shown in Figure 2.

I-V characteristics of PV module [25] [26] can be represented as:

where,

Different Parameters:

・ I_s is the current generated by the incident light.

・ I_o is the reverse saturation current.

・ q is the electron charge [1.60217646 × 10⁻¹⁹ C].

・ k is the Boltzmann constant [1.3806503 × 10⁻²³ J/K].

・ T [K] is the temperature of the p-n junction.

・ A is ideality factor of diode.

・ V_T is the thermal voltage of the module.

・ R_s is the series resistance of the module.

・ R_p is the parallel resistance of the module.

From Equation (1), the output voltage of PV module can be derived as follows:

Multiplying Equation (2) by I_pv, the output power of PV module can be obtained,

From Equation (1) to Equation (3), it is observe that the I_pv, V_pv, and P_pv are usually considered as pure DC values. However, in practical applications, the output voltage and current of PV module contain ripple components caused by the front-end converter of the system and this may cause significant impact on the output power. Hence appear the urgency to use a ripple reduction technique with the PV module.

Figure 3 shows PV output power perturbation caused by periodical ripple current. From Figure 3, periodically variation of p_pv due to periodical variation of i_pv, can easily be observed. As an illustration, consider a switching period from t = 0 to t = T_s for the case when PV module is operated near MPP assuming the irradiance is fixed as shown in Figure 3(b). When the active switch is turned on, i_pv will increase from I_a to I_b for t Î [0, DT_s]. At the same time, the corresponding p_pv trajectory is varied from P_a to P_b. It is seen that during this interval, the MPP is achieved only at one point [13] .

Similarly, when the switch is turned off, i_pv will decrease from I_b to I_a for t Î [DT_s, T_s]. The corresponding p_pv is varied from P_b to P_a. Again, the MPP is achieved only at one point. Obviously, from Figure 3(b) it is clearly seen that the average power P_PV,_avrg is less than the available maximum PV output power P_M.

To analyze the ripple-affected power loss of PV module, at first, the i_pv can be defined as a periodically time-variant function as i_pv(t).

・ I_PV,r(t) represents the current in the rising period.

・ I_PV,f(t) represents the current in the falling period.

・ I_PV,avrg represents the average value of PV current.

・ ∆i_PV is the ripple current.

・ D is the duty ratio.

・ T_s is the switching period.

For rise time,

For fall time,

Periodically time-variant function of the PV output power can be described as:

Then, substituting Equation (4) and Equation (5) into Equation (3), P_PV,r(t) and P_PV,f(t) can be derived as follows:

where, &

where, &.

Equation (6) and Equation (7) exhibits the presence of current ripple (∆i_PV) in the output power of PV module for both rise time and fall time. Thus the need for ripple cancelling technique is arrived to solve this dilemma of PV module.

PRCC are integrated into the input side of a conventional converter to eliminate the input current ripple. PRCC consists of a high frequency transformer modelling as an ideal transformer with turns ratio N and a magnetizing inductor Lm, a ripple mirror inductor L_r1 as well as two blocking capacitors C_r1, C_r2 that are connected to the primary and the secondary winding of the transformer respectively.

In addition, each terminal of the proposed PRCC is connected to one of the main inductor L₁ terminals of the converter where the current ripple is generated. Due to the blocking capacitors of C_r1 and C_r2 as well as the reversal polarity of the transformer, only the high frequency ac voltage/current of inductor L₁ are reflected to L_r1 automatically.

Wave shapes of Figure 5 demonstrate the working fundamental of PRCC. It can be observed that when the switch S is turned on, i_L1 exhibits a positive slope while i_Lr1 exhibits a negative slope. When the switch S is turned off, i_L1 exhibits a negative slope while i_Lr1 exhibits a positive slope. Thus mirror inductor attenuates input current ripple [13] .

Equation of Input current ripple cancelling ratio is:.

Figure 6 illustrates three operating states of the proposed system.

・ In state 1, the PV array supplies power to load and possibly also to the battery, corresponding to the daytime operation of the PV system.

・ In state 2, converter and loads are disconnected and the system enters into the stand-alone approach. The PV array charges battery without energy transferred to the load.

・ In state 3, the battery supplies power to the load through the converter, indicating the nighttime operation of the stand-alone system.

Mode I (Figure 7):

Switch S₁, S₂ are turned on and S₃, S₄ and S₅ are turned off. Converter acts as the modified version of SEPIC [27] [28] providing high output voltage.

In this state, capacitor is being involved in the operation of the converter through S₁ and S₂ switches. Effect of resistance R₂ is isolated from the circuit by turning off switch S₃.

・ State I: Switch M₂ is turned-on and the diode D₁ is blocked and the inductors L₁ and L₂ store energy. The input voltage is applied to the input inductor L₁ through switch M₂. C₂, L₂ and C₁ complete a circuit without changing the direction of inductor current. Load is connected directly with output capacitor C_o.

・ State II: Switch M₂ is turned-off and the energy stored in the input inductor L₁ is transferred to the output through the capacitor C₁ and output diode D₁, and also to the capacitor C₂ through the diode D₂. Therefore, the switch voltage is equal to the capacitor C₂ voltage. The energy stored in the inductor L₂ is transferred to the output through the diode D₁.

Mode II (Figure 8):

Switch S₁, S₂ are turned off and S₃, S₄ and S₅ are turned on. Converter acts as the conventional SEPIC [29] [30] converter. This state provides comparatively less step up ratio than mode I.

In this state of operation, diode D₂ is always reverse-biased and capacitor C₂ is being isolated by switch S₁ and S₂, as well as it will complete a circuit with R₂ through switch S₃. Load resistance will be reduced by removing R_L2 with the help of switch S₅.

・ State I: Switch M₂ is turned on, current i_L1 increases and the current i_L2 goes more negative. The capacitor C₁ supplies the energy to increase the magnitude of the current in i_L2, diode D₁ and D₂ are reverse-biased. C_o supplies energy to the load R_L1.

・ State II: Switch M₂ is turned off. Current i_Ct becomes the same as the current i_L1. Inductors do not allow instantaneous changes in current. Power is delivered to the load from both L₂ and L₁. However C₁ is being charged by L₁ during this off cycle, and will in turn recharge L₂ during the on cycle.

Proposed topology of multiple output levels are being described in next sub section. The motivation of this study is to design a dual mode- multiple output (DMMO) converter for increasing the conversion efficiency and voltage gain, reducing the control complexity, and saving the manufacturing cost.

Gate pulses Go2, Go3 and Go4 are the respective switching pulses for switches Mo2, Mo3 and Mo4, shown in Figure 9, as well as they are provided fixed duty cycle of 80%, 50% and 30% subsequently. In Figure 10, four operating states are illustrated.

State I (T₀ − T₁): In this state, switches Mo2, Mo3 and Mo4 are turned ON for a span. Along with these diodes Do2, Do3 and Do4 are being turned OFF. Three levels are directly connected to the converter.

State II (T₁ − T₂): In this state, switches Mo2, Mo3 are turned ON and diodes Do2, D03 are turned OFF. For this span, switch Mo4 is turned OFF. Because of the polarity of inductor Lo4, diode Do4 turns ON and the output loop is connected to the inductor Lo4 through the diode Do4.

State III (T₂ − T₃): Only switch Mo2 is turned ON and the corresponding diode Do2 is turned OFF. From multiple levels only the first level is directly connected with the

converter circuit. Other two levels are connected to inductors Lo3 and Lo4 respectively, through corresponding diodes.

State IV (T₃ − T₄): Output loops are completed individually through respective inductors and diodes as all the three switches are being turned OFF.

The maximum power point tracking (MPPT) can be implemented by adjusting the duty cycle of switching device M₁ shown in Figure 4. In the MPPT loop, the PV voltage is regulated to follow an optimal operating point, which is initially assigned to 80% of the open-circuit voltage of the PV array. This point can be determined by the “constant voltage method”. Moreover, the PV voltage regulation loop is used to improve the MPPT performance.

In Mode I, switch S₁, S₂ are turned on and S₃, S₄ and S₅ are turned off, when the converter act as modified SEPIC. On/off operation of these switches are complementary for mode II, when it acts as conventional SEPIC.

In the output voltage control loop shown, the duty cycle of switching device M₂ shown in Figure 4 is the control variable, which regulates the output voltage to follow the expected voltage. To serve this purpose PI controller is used. When the output power of the PV array is lower than the load power, the battery should supply the difference. Here a single control scheme can regulate multiple output levels. The control block diagram of the proposed control scheme is illustrated in Figure 11.

Ø Constant Voltage Method:

The solar array is temporarily isolated from the MPPT, and a V_OC measurement is taken [31] . Next, the MPPT calculates the correct operating point using the equation mention below:

And the pre-set value of K, and adjusts the array’s voltage until the calculated V_MPP is reached. This operation is repeated periodically to track the position of the MPP. Although this method is extremely simple, it is difficult to choose the optimal value of the constant K. Value of ranging from 73% to 80% [32] [33] . Figure 12 shows the actual K values required for a given PV array over a temperature range of 0˚C - 60˚C and irradiance levels from 200 to 1000 W/m². These curves were calculated using the I?V relationship for a PV cell.

Ø Proportional Integral Controller:

The PI-Controller is a combination of a proportional and integral controller, which has two tuning parameters to adjust: proportional (kp) and integral (ki). PI controller is mainly used to eliminate the steady state error resulting from P controller [35] Figure 13 demonstrates the operating fundamentals of PI controller through block diagram.

where , ∆ = set point(SP) - process variable(PV)

CO = controller output signal

The integral term continually sums up error. Through constant summing, integral action accumulates influence based on how long and how far the measured PV has been from SP over time.

v Effect of (k_p):

・ Increasing k_p will reduce the steady state error.

・ After certain limit increasing k_p only causes overshoot.

・ Increasing k_p reduces the rise time [36] .

v Effect of (k_i):

・ Integral control eliminates the steady state error.

・ After certain limit, increasing k_i will only increase overshoot.

・ Increasing k_i reduces the rise time a little.