The conventional converters have many blockades, such as high distortion, losses with a variation at the amplitude of the output during faulty conditions. To overcome the limitations and problems of the traditional converters, an impedance-source (or impedance-fed) power converter (that can be abbreviated as ZSC) is introduced. Figure 1 depicts the general structure of ride through strategy introduced in the dual ZSI. The ZSI is a special impedance network (or circuit) that connects the voltage source converter and current converter, main circuit to the power source, load, or another converter, for providing special features that cannot be seen in the conventional converters [1] [2] .

Contemporarily, three-level inverters are extensively used for industrial applications due to their many inherent advantages including a lower electromagnetic interference (EMI), better waveform quality and lower semiconductor stress which are achieved by an appropriate series-connection of multiple static switches. Despite this popularity, a possible complication associated with three-level inverters is higher risk of experiencing semiconductor switching failure (both open and short circuit). As more switches are used for the inverter construction the switching failure is inevitable [3] [4] .

For enhancing the inverter ride-through capability, many fault-tolerant schemes have been proposed with some solutions focusing on the timely replacement of faulty switches using extra pre-installed switches and others focusing on the appropriate selection of switching states that can give rise to a lower waveform distortion. This paper proposed three-level Z-source inverters with raid through capability [5] - [9] , unlike other traditional three-level inverter where raid through is not supported.

Here in this manuscript all three-level Z-source inverters can ride-through semiconductor failure smoothly with their output-waveform quality and amplitude kept nearly unchanged. These performance improvements are achieved by performing slight reconfiguration of the inverter state sequences and gating arrangements with no additional hardware requirements as shown in Figure 1.

There are many types of ZSI, which have been used for different applications. The few are explained here for the fault tolerant strategy. They are, Z-source neutral point clamped inverter with two dc sources, Z-source neutral point clamped inverter with single dc sources, Z-source DC-linked cascaded inverter, Dual Z-source inverter with two dc sources, Dual Z-source inverter with single dc sources [10] - [12] . But the schemes for detecting faults are not topologically dependent, meaning that existing detection schemes can also be used for new inverter topologies with only minor modifications.

Compared with the other types of inverter it is palpable that the dual source inverter is mostly used, because of its less common mode voltage and it can also be completely eliminated using ride through strategy. The dual-inverter topologies are that the switches are functionally identical with no distinction like inner and outer switch classifications found. The same technique has been used for identifying open-circuit switches in three-level inverter in [9] with some extra logics added to distinguish the four switches per phase. Other more advanced techniques are proposed in [10] for diagnosing faults in a multilevel inverter that are referred for this paper. With the earlier belief in view, this paper presents a detailed study of a fault ride-through scheme with slight modifications in Figure 2.

Additionally, for cases where the dual Z-source inverters are used and configured to operate with reduced common mode switching [13] , the simple reconfiguration of the inverter gating signals would allow the inverters to continue operating with less common-mode voltage.

The dual Z-source inverters can be supplied by either two isolated dc sources or a single source. In spite of their drawbacks including the control complexity in the existing method a new technique is implemented with slight modifications in Figure 3. Both inverters are tuned to operate with zero common-mode voltage by simply restricting their switching states (by the omitting the dead time delay, which is an inherent feature of all Z-source inverters). Generally there are two categories for reducing the CMV they are using hardware devices like isolation transformer, filters, zero sequencing impedance and control strategy using software includes SVPWM schemes, sine PWM scheme etc. Here the dual-inverter topology triacs connected in series with the inverters controlled by SPWM technique is introduced.

As triac is a bidirectional device it can conduct in both directions. The ride-through technique for dual Z-source inverters can simply be performed by considering the open and short-circuit failure of any single switch which leads to common mode voltage. The term common mode voltage is defined as an undesirable electric signal which is generated by the power electronic switching circuits having same amplitude and frequency to

that of the reference signal. This interferes with the control and other electronic equipments. Hence leads to EMI, high shaft voltage. When this voltage exceeds the breakdown voltage results in large bearing current, and causes premature failure of the motor bearing, induces leakage current, false tripping of relays etc. Hence it is a great issue which exists only in motor forming a crisis in the system.

Hence, during switching failure the inverter simply generates two level output without altering its shoot-through duration for compensating the voltage dip. This method turns all the zero states into shoot through state thus minimizing the voltage stress across the switches. Where Sa, Sb, and Sc represent the switching functions of inverter U in two-level mode and Vi is its dc-link voltage. The proposed scheme is likely to work under most operating conditions except for cases whereby two switches and their accompanied anti-parallel diodes in a phase leg in either of the inverter U or G fail, open-circuit simultaneously.

Assuming that a fault occurred in inverter G, the failed terminal Vx(y) (x = a, b, or c, and y = U or G) becomes isolated, by forcing it to null state [000] or [111] by turning off the lower triacs, the aroused floating point will be symmetrical which can no longer be formed for common-mode voltage elimination and that no current can now flow in the faulted phase. In addition, for the case where two isolated sources can be used, it is noted that the output terminals of the lower inverter G are now constantly shorted to form a floating point on the primary side of the transformer.

The generated common-mode voltage at the secondary terminals of the transformer is derived, whose value is zero. This extra feature and the symmetrical structure of the dual inverter allow it to ride-through virtually all types of semiconductor failure with negligible disturbances incurred on its output-voltage amplitude, waveform quality, and common mode elimination capability, which, to date, cannot be achieved by other three-level Z-source inverters. In the erstwhile methods zero common mode voltage cannot be retained if a single dc source is used in the inverter. This proposed technique can be explained through two modes of operations.

They are,

Mode 1: Pre-fault condition

Mode 2: Faulted condition

The proposed fault-tolerant strategies were initially verified in mat lab simulation with the Z-source network parameters chosen as C = 2200 μF and L = 5 mH and the switching frequency set to 5 kHz. In common, all tested inverters were powered from single dc sources with set to 40 V, which was subsequently boosted to ≈100 V for powering the rear-end inverter circuitry during various fault conditions set to occur at t = 40 ms. Before fault occurrence, the pre-fault control parameters are set to M = 1 and T0/T = 0, and immediately upon sensing the fault, the control parameters are returned to M = 0.67 and T0/T = 0.33 is needed for producing enough voltage boosting to keep the three-phase ac output currents unchanged. Hence the Phase and line voltage is of about 230 V during normal and faulted condition.

The Z-source inverter is specially suited for fuel cell applications. Unique features include buck-boost inversion by single power-conversion stage, improved reliability, strong EMI immunity, and low EMI. The Z-source technology can be applied to the entire spectrum of power conversion. To have a new power conversion technology, a new Z-source inverter is proposed which has the capacity to solve the above problems and unique feature includes,

Ÿ It can boost the output voltage by introducing shoot through operation mode, which is forbidden in traditional voltage source inverters.

Ÿ With this unique feature, the Z-source inverter provides a cheaper, simpler, single stage approach for applications of fuel cell.

Thus, the Z-source inverter system can minimize stress and increase the output power greatly. The simulated results obtained with the same pre- and post-fault parameters of M = 1 and T0/T = 0. Since the faulted circuitry is still being powered by the two separate dc sources, instead of one as in the first case (Figures 6-9).

However, it causes shoot through duty ratio to vary in each cycle, thus increasing the ripple content in inductor current. When the output frequency is low, the inductor ripple becomes significant and a large inductor is required. This method achieves maximum boosting output while keeping shoot through duty ratio as constant all the time, thus reduces ripple content in inductor current.

The Figure 9 shows the hardware image of the dual ZSI using triacs. The components are enumerated in Table 1 and Table 2 with their specifications. The Figure 10 and Figure 11 show the output of the hardware under normal and faulty condition which are displayed using the digital oscilloscope.

In this project a new ride through strategy for Dual ZSI using triac is analyzed and the output has been simulated using MATLAB software. Its feasibility is checked with the simulated results of the conventional method. The fault condition is detected within one fourth of the fundamental cycle. This concept improves the ride-through ability of the dual Z-source inverters supplied by either a single dc source or two isolated dc sources with added triacs, with an advantage of maximum output, fewer ripple content and zero common mode voltage; hence helps the inverter to operate without any interruption. The future scope of this Impedance Source Inverter is that, by obtaining the parameter control of the motor this can be implemented in speed control methods and can be achieved by using micro controller as a feedback between output and the input.

Nazar Ali, A. and Jeyabharath, Dr.R. (2016) Ride through Strategy for a Three-Level Dual Z-Source Inverter Using TRIAC. Circuits and Systems, 7, 3911-3921. http://dx.doi.org/10.4236/cs.2016.711326