<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE article  PUBLIC "-//NLM//DTD Journal Publishing DTD v3.0 20080202//EN" "http://dtd.nlm.nih.gov/publishing/3.0/journalpublishing3.dtd"><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" dtd-version="3.0" xml:lang="en" article-type="research article"><front><journal-meta><journal-id journal-id-type="publisher-id">CS</journal-id><journal-title-group><journal-title>Circuits and Systems</journal-title></journal-title-group><issn pub-type="epub">2153-1285</issn><publisher><publisher-name>Scientific Research Publishing</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.4236/cs.2016.79189</article-id><article-id pub-id-type="publisher-id">CS-68330</article-id><article-categories><subj-group subj-group-type="heading"><subject>Articles</subject></subj-group><subj-group subj-group-type="Discipline-v2"><subject>Computer Science&amp;Communications</subject><subject> Engineering</subject><subject> Physics&amp;Mathematics</subject></subj-group></article-categories><title-group><article-title>
 
 
  New DCM Operated Single Phase Bridgeless Cuk Derived Converters for Power Factor Correction
 
</article-title></title-group><contrib-group><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>P.</surname><given-names>M. Dhanasekaran</given-names></name><xref ref-type="aff" rid="aff1"><sup>1</sup></xref><xref ref-type="corresp" rid="cor1"><sup>*</sup></xref></contrib><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Parasunath</surname><given-names>Veena</given-names></name><xref ref-type="aff" rid="aff2"><sup>2</sup></xref></contrib><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Rajaiah</surname><given-names>Jeyabharath</given-names></name><xref ref-type="aff" rid="aff2"><sup>2</sup></xref></contrib></contrib-group><aff id="aff2"><addr-line>Department of EEE, KSR Institute for Engineering and Technology, Thiruchengode, Tamil Nadu, India</addr-line></aff><aff id="aff1"><addr-line>Department of EEE, K. S. Rangasamy College of Technology, Thiruchengode, Tamil Nadu, India</addr-line></aff><author-notes><corresp id="cor1">* E-mail:<email>drnrbals@gmail.com(PMD)</email>;</corresp></author-notes><pub-date pub-type="epub"><day>05</day><month>07</month><year>2016</year></pub-date><volume>07</volume><issue>09</issue><fpage>2176</fpage><lpage>2188</lpage><history><date date-type="received"><day>2</day>	<month>May</month>	<year>2016</year></date><date date-type="rev-recd"><day>accepted</day>	<month>20</month>	<year>May</year>	</date><date date-type="accepted"><day>14</day>	<month>July</month>	<year>2016</year></date></history><permissions><copyright-statement>&#169; Copyright  2014 by authors and Scientific Research Publishing Inc. </copyright-statement><copyright-year>2014</copyright-year><license><license-p>This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/</license-p></license></permissions><abstract><p>
 
 
  This paper presents a power factor corrected (PFC) new bridgeless (BL) Cuk Topologies for low power applications. A BL configuration of Cuk converter is proposed which eliminates the usage of diode bridge rectifier at the front end of the PFC converter, thus reducing the switching and conduction losses coupled with it. This new BL Cuk converter has two semiconductors switches. The current flow during each switching cycle interval of the converter reduces the conduction losses compared to the conventional Cuk PFC converter. It also reduces the input current ripple and Electromagnetic Interference (EMI). The inrush current during the starting period is limited and the input, output currents of the converter are continuous with minimum current ripple. Hence it is preferred mostly compared to other PFC circuits. The proposed topology works in the Discontinuous Conduction Mode (DCM) with simple control circuitry to achieve almost a unity power factor with less distortion in the input AC current. The switching of the power switches is done under zero current. The proposed PFC topologies are theoretically investigated and performance comparisons are made with the conventional rectifiers. The proposed PFC converter is simulated in MATLAB/SIMULINK with Fuzzy Logic Controller (FLC) and results are demonstrated to evaluate the effectiveness of the controller.
 
</p></abstract><kwd-group><kwd>Bridgeless (BL) Cuk Converter Topology</kwd><kwd> Power Factor Correction (PFC)</kwd><kwd> Total Harmonic Distortion (THD)</kwd><kwd> Fuzzy Logic Controller (FLC)</kwd></kwd-group></article-meta></front><body><sec id="s1"><title>1. Introduction</title><p>The active power factor correction circuits for low and medium power applications have been increasing in recent years [<xref ref-type="bibr" rid="scirp.68330-ref1">1</xref>] , [<xref ref-type="bibr" rid="scirp.68330-ref2">2</xref>] with the choice of research to improve the power quality according to the harmonic regulations and standards. Conventionally, most of the active PFC circuits comprises of a front end diode bridge rectifier (DBR) which distorts the utility line voltage. This reduces the supply power factor and also the optimized usage of utility system [<xref ref-type="bibr" rid="scirp.68330-ref3">3</xref>] . Referring to the conventional PFC in <xref ref-type="fig" rid="fig1">Figure 1</xref>, in switch ON-time, the current flows through two diodes in bridge rectifier and the power switch (Q).</p><p>During the switch OFF-time, current flows through another two diodes of DBR and the diode (D<sub>o</sub>) in the output side. Thus, in each switching cycle, three devices are conducted and result in significant conduction losses due to the forward voltage drop across the bridge diode. This degrades the rectifier’s efficiency especially at a low input voltage.</p><p>In order to maximize the rectifier efficiency, many research works have been directed towards designing the bridgeless PFC converters with the elimination of Diode Bridge at the front end [<xref ref-type="bibr" rid="scirp.68330-ref3">3</xref>] . The current in this bridgeless PFC converter is made to flow in minimum number of switches. Accordingly, the conduction losses can be reduced and efficiency can be improved. Recently in the literature, there are several bridgeless PFC rectifiers that have been introduced for step-up/step-down applications. The most frequently used topology is the bridgeless boost PFC rectifier because of its low cost and high efficiency. It has some major practical drawbacks such as, starting inrush currents, difficulties in input/output isolations, output voltage higher than the peak input voltage, lack of current limitation in overload conditions.</p><p>In a bridgeless single ended primary inductance converter (SEPIC) converter, the output current is discontinuous with high ripple content. A bridgeless buck PFC converter for step down voltage applications was proposed. However, this buck PFC converter has high total harmonic distortion (THD) [<xref ref-type="bibr" rid="scirp.68330-ref4">4</xref>] , [<xref ref-type="bibr" rid="scirp.68330-ref5">5</xref>] and low power factor. The next topology for PFC applications is the Cuk PFC converter. It offers several advantages such as natural protection against start-up in rush current, less current ripple at input side, less electromagnetic interference (EMI) in Discontinuous Conduction Mode (DCM) [<xref ref-type="bibr" rid="scirp.68330-ref6">6</xref>] - [<xref ref-type="bibr" rid="scirp.68330-ref8">8</xref>] . The input and output currents are continuous with low ripples compared to SEPIC PFC converter [<xref ref-type="bibr" rid="scirp.68330-ref9">9</xref>] - [<xref ref-type="bibr" rid="scirp.68330-ref14">14</xref>] . Thus, the bridgeless Cuk converter is a potential candidate compared over the basic PFC topologies, especially for low power applications. In this paper, the bridgeless Cuk PFC converter topologies are taken and their performances are analyzed. A comparison is made against the efficiency, power factor correction and reduction in THD for all the Cuk PFC rectifiers.</p></sec><sec id="s2"><title>2. Types of Bridgeless Cuk PFC Rectifiers</title><p>The Bridgeless Cuk PFC rectifiers are shown in the Figures 2(a)-(c). There are three topologies, viz., Type-1, Type-2, and Type-3 Cuk PFC rectifiers. These topologies are configured by connecting the two DC-DC Cuk converters, each one for the half period of the supply voltage. The circuit operations of the three topologies during positive and negative half periods are shown in Figures 3(a)-(f). Note in Figures 3(a)-(f) the current flow paths are in one or two semiconductors and hence the current stresses through the switches are reduced. Thus</p><fig id="fig1"  position="float"><label><xref ref-type="fig" rid="fig1">Figure 1</xref></label><caption><title> Conventional Cuk PFC converter</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x7.png"/></fig><fig-group id="fig2"><label><xref ref-type="fig" rid="fig2">Figure 2</xref></label><caption><title> Bridgeless Cuk PFC converters. (a) Type-1; (b) Type-2; (c) Type-3.</title></caption><fig id ="fig2_1"><label>(b)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x8.png"/></fig><fig id ="fig2_2"><label>(c)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x9.png"/></fig><fig id ="fig2_3"><label></label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x10.png"/></fig></fig-group><fig-group id="fig3"><label><xref ref-type="fig" rid="fig3">Figure 3</xref></label><caption><title> (a) &amp; (b) Positive half and negative half cycle operation of Type-1; (c) &amp; (d) Positive half and negative half cycle operation of Type-2; (e) &amp; (f) Positive half and negative half cycle operation of Type-3.</title></caption><fig id ="fig3_1"><label>(b)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x11.png"/></fig><fig id ="fig3_2"><label>(c)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x12.png"/></fig><fig id ="fig3_3"><label>(d)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x13.png"/></fig><fig id ="fig3_4"><label>(e)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x14.png"/></fig><fig id ="fig3_5"><label>(f)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x15.png"/></fig><fig id ="fig3_6"><label></label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x16.png"/></fig></fig-group><p>improving the efficiency compared to conventional Cuk PFC rectifiers. The output bus for the type 1, type 3 converter is connected with the supply side through the slow recovery diodes D<sub>p</sub> and D<sub>n</sub> (<xref ref-type="fig" rid="fig2">Figure 2</xref>(a) and <xref ref-type="fig" rid="fig2">Figure 2</xref>(c)) and in the type 2 topology (<xref ref-type="fig" rid="fig2">Figure 2</xref>(b)), it is directly connected. Thus, these PFC configurations are a resistant for common mode EMI.</p><p>The rectifiers uses two power switches Q<sub>1</sub> and Q<sub>2</sub>. The control circuit for the Cuk rectifiers is simple since, both the switches are driven by the same control signal. The usage of inductor compared to the conventional topology is a drawback in terms of cost, but it improves the thermal performance. In addition, these topologies provide near zero ripple current at the input and output side of the PFC converter.</p></sec><sec id="s3"><title>3. Operation of Cuk PFC Rectifier</title><p>The Type-3 Cuk PFC rectifier is taken for analysis and its operational performance is studied. This converter is assumed to be operating at steady state condition and it follows the assumptions like ideal loss less components, pure sinusoidal AC voltage and all the capacitors are large such that there is no voltage ripples during the period T<sub>s</sub>. Referring to <xref ref-type="fig" rid="fig3">Figure 3</xref>(e), during the positive half period of supply voltage, is the first DC-DC Cuk circuit L<sub>1</sub>-Q<sub>1</sub>-C<sub>1</sub>-L<sub>o</sub><sub>1</sub>-D<sub>o</sub><sub>1</sub>, is active through diode D<sub>p</sub> and is connects the input source to Output port. During the negative half period shown in <xref ref-type="fig" rid="fig3">Figure 3</xref>(f), the second Cuk circuit, L<sub>2</sub>-Q<sub>2</sub>-C<sub>2</sub>-L<sub>o</sub><sub>2</sub>-D<sub>o</sub><sub>2</sub>, is active through diode D<sub>n</sub> and connects the input source to output end. Thus, in both periods the AC supply source reaches the output ports.</p><p>There are three topological modes of operation for Type-3 Cuk rectifier in DCM operation during one switching stage T<sub>s</sub>. The operating stages over a switching cycle are described as follows.</p><sec id="s3_1"><title>3.1. Stage 1 Operation [t<sub>0</sub>, t<sub>1</sub>]</title><p>This stage of operation starts when the Q1 ON in the interval t<sub>0</sub> to t<sub>1</sub>, as shown in <xref ref-type="fig" rid="fig4">Figure 4</xref>. The inductor current i<sub>L</sub><sub>1</sub> forward biases the Diode D<sub>p</sub> and the diode D<sub>n</sub> is reverse biased by the input voltage. The reverse voltage (V<sub>ac</sub> + V<sub>o</sub>) reverse biases the output diode D<sub>o</sub><sub>1</sub> and at the same time, D<sub>o</sub><sub>2</sub> is reverse biased by the output voltage V<sub>o</sub>.</p><p>In this mode, the inductor currents i<sub>L</sub><sub>1</sub> and i<sub>Lo</sub><sub>1</sub> increase linearly with the input voltage, while due to the constant voltage across C<sub>2</sub>, the current through L<sub>o</sub><sub>2</sub> is zero. The various inductor currents during this stage 1 time interval is shown in <xref ref-type="fig" rid="fig5">Figure 5</xref>.</p><p>The peak current flowing through the active switch Q<sub>1</sub> is given by</p><disp-formula id="scirp.68330-formula93"><label>(1)</label><graphic position="anchor" xlink:href="http://html.scirp.org/file/9-7600909x17.png"  xlink:type="simple"/></disp-formula><p>where V<sub>m</sub> is the peak amplitude of the supply voltage, D<sub>1</sub> is the duty cycle for power switch and L<sub>e</sub> is the parallel combination of inductors L<sub>1</sub> and L<sub>o</sub><sub>1</sub> respectively.</p><fig id="fig4"  position="float"><label><xref ref-type="fig" rid="fig4">Figure 4</xref></label><caption><title> Stage 1 operation of Type-3 converter</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x18.png"/></fig><fig id="fig5"  position="float"><label><xref ref-type="fig" rid="fig5">Figure 5</xref></label><caption><title> DCM waveforms of the converter for one switching period from t<sub>0</sub> to T<sub>s</sub></title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x19.png"/></fig></sec><sec id="s3_2"><title>3.2. Stage 2 Operation [t<sub>1</sub>, t<sub>2</sub>]</title><p>This mode starts when the switch Q1 turns OFF between the time interval of t<sub>1</sub> to t<sub>2</sub> and the diode D<sub>o</sub><sub>1</sub> is turned ON. Thus it provides a flow path for the inductor currents i<sub>L</sub><sub>1</sub> and i<sub>Lo</sub><sub>1</sub> as shown in <xref ref-type="fig" rid="fig6">Figure 6</xref>. The diode D<sub>p</sub> remains in conducting state to provide a path for i<sub>L</sub><sub>1</sub>.</p><p>In this interval, Diode D<sub>o</sub><sub>2</sub> remains in reverse biased condition. The interval ends when i<sub>Do</sub><sub>1</sub> reaches zero and thus a zero current turn OFF.</p></sec><sec id="s3_3"><title>3.3. Stage 3 Operation [t<sub>2</sub>, t<sub>3</sub>]</title><p>The stage 3 operation starts at t<sub>2</sub> and ends at t<sub>3.</sub> During this interval, the diode D<sub>p</sub> conducts and provide a flow path for i<sub>L</sub><sub>1</sub> as shown in <xref ref-type="fig" rid="fig7">Figure 7</xref>. The inductors of the Cuk rectifiers, in this interval perform as constant current sources.</p><p>The voltage across the three inductors in this interval is zero and the current i<sub>L</sub><sub>1</sub> charges capacitor C<sub>1</sub>. When switch Q1 is turned ON, the duration of this stage is ended.</p></sec></sec><sec id="s4"><title>4. Simulation Study of Type 3 Cuk Converter</title><p>To verify the feasibility of type 3 bridgeless Cuk PFC, simulation model is designed using MATLAB/ SIMULINK and it is shown in <xref ref-type="fig" rid="fig8">Figure 8</xref>. The PFC operation of the circuit under DCM mode is controlled by Fuzzy logic controller and the harmonics is controlled by voltage follower control approach.</p>Fuzzy Logic Controller Based BL Cuk Rectifier<p>The <xref ref-type="fig" rid="fig8">Figure 8</xref> shows the MATLAB simulation circuit of BL Cuk rectifier controlled by fuzzy logic controller (FLC). This FLC uses the Mamdani fuzzy inference system [<xref ref-type="bibr" rid="scirp.68330-ref15">15</xref>] - [<xref ref-type="bibr" rid="scirp.68330-ref20">20</xref>] and it has the following parameters.</p><p> Triangular membership functions for both Input and output variables.</p><p> Fuzzification using continuous universe of discourse.</p><p> Implication function using the “min” operator.</p><p> Defuzzification using the “centroid” method.</p><p>The inputs of the FLC are error and change in error voltage. <xref ref-type="fig" rid="fig9">Figure 9</xref> shows the input and output triangular membership function assigned for the work of power factor correction.</p><p><xref ref-type="table" rid="table1">Table 1</xref> includes five linguistic variables for error voltage and for changing error voltage. They are Zero (Z), Negative Big (NB), Negative Small (NS), Positive Big (PB), and Positive Small (PS). The 25 fuzzy rules are made using the input variables and are as follows:</p><fig id="fig6"  position="float"><label><xref ref-type="fig" rid="fig6">Figure 6</xref></label><caption><title> Stage 2 operation of Type-3 Cuk converter</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x20.png"/></fig><fig id="fig7"  position="float"><label><xref ref-type="fig" rid="fig7">Figure 7</xref></label><caption><title> Stage 3 operation of Type-3 Cuk PFC converter</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x21.png"/></fig><table-wrap id="table1" ><label><xref ref-type="table" rid="table1">Table 1</xref></label><caption><title> Fuzzy rule table</title></caption><table><tbody><thead><tr><th align="center" valign="middle"  colspan="2"   rowspan="2"  ></th><th align="center" valign="middle"  colspan="5"  >E</th></tr></thead><tr><td align="center" valign="middle" >NB</td><td align="center" valign="middle" >NS</td><td align="center" valign="middle" >Z</td><td align="center" valign="middle" >PS</td><td align="center" valign="middle" >PB</td></tr><tr><td align="center" valign="middle"  rowspan="5"  >∆e</td><td align="center" valign="middle" >NB</td><td align="center" valign="middle" >NB</td><td align="center" valign="middle" >NB</td><td align="center" valign="middle" >NB</td><td align="center" valign="middle" >NS</td><td align="center" valign="middle" >Z</td></tr><tr><td align="center" valign="middle" >NS</td><td align="center" valign="middle" >NB</td><td align="center" valign="middle" >NS</td><td align="center" valign="middle" >NS</td><td align="center" valign="middle" >Z</td><td align="center" valign="middle" >PS</td></tr><tr><td align="center" valign="middle" >Z</td><td align="center" valign="middle" >NB</td><td align="center" valign="middle" >NS</td><td align="center" valign="middle" >Z</td><td align="center" valign="middle" >PS</td><td align="center" valign="middle" >PB</td></tr><tr><td align="center" valign="middle" >PS</td><td align="center" valign="middle" >NS</td><td align="center" valign="middle" >Z</td><td align="center" valign="middle" >PS</td><td align="center" valign="middle" >PS</td><td align="center" valign="middle" >PB</td></tr><tr><td align="center" valign="middle" >PB</td><td align="center" valign="middle" >Z</td><td align="center" valign="middle" >PS</td><td align="center" valign="middle" >PB</td><td align="center" valign="middle" >PB</td><td align="center" valign="middle" >PB</td></tr></tbody></table></table-wrap><fig id="fig8"  position="float"><label><xref ref-type="fig" rid="fig8">Figure 8</xref></label><caption><title> BL Type-3 Cuk PFC converter with fuzzy logic controller</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x22.png"/></fig><fig-group id="fig9"><label><xref ref-type="fig" rid="fig9">Figure 9</xref></label><caption><title> Input and output triangular membership functions.</title></caption><fig id ="fig9_1"><label></label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x23.png"/></fig><fig id ="fig9_2"><label></label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x24.png"/></fig><fig id ="fig9_3"><label></label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x25.png"/></fig></fig-group><p>If (e is A<sub>i</sub>) and (Δe is B<sub>i</sub>) then (u is Y<sub>i</sub>)</p><p>Where, e and Δe provides error voltage and the change in error voltage. u is the output from the fuzzy logic controller which is used for switching the power switches of Cuk converter. A<sub>i</sub>, B<sub>i</sub> is the input membership functions of the FLC and Y<sub>i</sub> output membership function. By using the inference method as min operator and defuzzification by centroid formula for weighting all the fuzzy rule contributions, the controlled crisp value is obtained to operate the switches in the BL Cuk converter. This gives the input power factor correction.</p></sec><sec id="s5"><title>5. Results and Discussion</title><p>The input voltage and current waveforms obtained from the SIMULINK software model of fuzzy Controlled Bridgeless Type-3 Cuk PFC rectifier are shown in <xref ref-type="fig" rid="fig1">Figure 1</xref>0 and <xref ref-type="fig" rid="fig1">Figure 1</xref>1. It is observed, a near sinusoidal supply current at the input side of PFC converter and it follows the supply voltage.</p><p>The input voltage to the simulation circuit is 100 Vrms (141 V peak to peak) and the type -3 BL Cuk converter work in DCM mode. The output voltage obtained is 50 V in buck operation and the output current is 3.3 Amps.</p><p><xref ref-type="fig" rid="fig1">Figure 1</xref>2 and <xref ref-type="fig" rid="fig1">Figure 1</xref>3 show the voltage and current waveforms taken at the output side after implementation of fuzzy controller. The framed fuzzy rules work on the Cuk converter and reduces the supply current THD. Thus it gives good power factor correction compared to the conventional controller.</p><p><xref ref-type="fig" rid="fig1">Figure 1</xref>4(a) shows the source current THD observed at the supply side of Cuk converters. The THD is within the tolerable limits of IEEE harmonic standards. <xref ref-type="fig" rid="fig1">Figure 1</xref>4(b) and <xref ref-type="fig" rid="fig1">Figure 1</xref>5(a) show the variation of power factor for different output power. The obtained power factor is nearer to unity for the proposed type 3 converter. <xref ref-type="fig" rid="fig1">Figure 1</xref>5(b) shows the efficiency with conventional and bridgeless Cuk rectifier configurations. Type-3 Cuk converter shows high efficiency compared to other conventional circuits and so, it is recommended for low power PFC applications.</p><fig id="fig10"  position="float"><label><xref ref-type="fig" rid="fig1">Figure 1</xref>0</label><caption><title> Input voltage waveform of fuzzy controlled Type-3 BL Cuk PFC converter</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x26.png"/></fig><fig id="fig11"  position="float"><label><xref ref-type="fig" rid="fig1">Figure 1</xref>1</label><caption><title> Input current waveform of fuzzy controlled Type-3 BL Cuk PFC converter</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x27.png"/></fig></sec><sec id="s6"><title>6. Conclusion</title><p>BL Cuk topologies based on fuzzy controller have been presented for power factor correction in this paper. The</p><fig id="fig12"  position="float"><label><xref ref-type="fig" rid="fig1">Figure 1</xref>2</label><caption><title> Output voltage waveform of fuzzy controlled Type-3 BL Cuk PFC converter</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x28.png"/></fig><fig id="fig13"  position="float"><label><xref ref-type="fig" rid="fig1">Figure 1</xref>3</label><caption><title> Output current waveform for fuzzy implemented Type-3 BL Cuk PFC converter</title></caption><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x29.png"/></fig><fig-group id="fig14"><label><xref ref-type="fig" rid="fig1">Figure 1</xref>4</label><caption><title> Comparative analysis. (a) Current THD and output power; (b) Power factor.</title></caption><fig id ="fig14_1"><label>(b)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x30.png"/></fig><fig id ="fig14_2"><label></label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x31.png"/></fig></fig-group><fig-group id="fig15"><label><xref ref-type="fig" rid="fig1">Figure 1</xref>5</label><caption><title> Comparative analysis. (a) Power factor and input voltages; (b) Efficiency and output power.</title></caption><fig id ="fig15_1"><label>(b)</label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x32.png"/></fig><fig id ="fig15_2"><label></label><graphic mimetype="image"   position="float"  xlink:type="simple"  xlink:href="http://html.scirp.org/file/9-7600909x33.png"/></fig></fig-group><p>validity of fuzzy controller and the performance of the topologies are verified by using MATLAB simulation. These BL topologies have been operated in DCM mode for achieving an inherent power factor correction at the supply side. For varied supply voltage, good dynamic performances have been attained with improved power quality limits of the harmonic standards. Moreover, the topologies can improve the efficiency by approximately about 1% in comparison to the conventional PFC circuits. The Type-3 Cuk converter shows better performance compared to other topologies and it is recommended for low power PFC applications.</p></sec><sec id="s7"><title>Cite this paper</title><p>P. M. Dhanasekaran,Parasunath Veena,Rajaiah Jeyabharath, (2016) New DCM Operated Single Phase Bridgeless Cuk Derived Converters for Power Factor Correction. Circuits and Systems,07,2176-2188. doi: 10.4236/cs.2016.79189</p></sec><sec id="s8"><title>NOTES</title></sec></body><back><ref-list><title>References</title><ref id="scirp.68330-ref1"><label>1</label><mixed-citation publication-type="other" xlink:type="simple">Tollik, D. and Pietkiewicz, A. (1992) Comparative Analysis of 1-Phase Active Power Factor Correction Topologies. 14th International Telecommunications Energy Conference, Washington DC, 4-8 October 1992, 517-523.   
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