One of the important objectives of detailed testing of VLSI (very large scale integration) circuits and systems is to make sure that there are no defects in the manufactured products, and that they meet the specifications. Further, the information generated during the testing may come of help in increasing the product yield via improvising the process technology by reducing the production cost.

The fabrication process of the integrated circuit has different steps including photolithography, printing, etching and doping. During manufacturing, each of these steps has its own flaws. These flaws may lead to failure in the operation of the individual ICs. VLSI technology has made the testing of ICs complex and time consuming resulting in the increased cost of the ICs. The problems related to testing have enormously intensified in case of SOC (System on Chip) because of the large numbers of IP (Intellectual Property) cores on a single silicon chip. This huge reduction in the circuit size has increased the sensitivity to performance variations and they still require complete testing before they are shipped to the customers. There is no denying of the fact that the overall quality of the final product is greatly improved through testing, though it has no bearing on the manufacturing caliber of the ICs. The testing ensures the imperfections of the product are detected only if it is implemented during the crucial stages of the development cycle. It can also be taken as an approach to validate the design and check the process involved.

The different IP cores of a SOC are not readily accessible because of the complexity of the SOC and inadequate test pins. However, one can increase the accessibility of a controllable or observable node in the circuit by applying the DFT (Design-For-Testability) strategies. These strategies decrease the test cost, increase the product’s quality, and make easy the design characterization and test program implementation. In order to test these systems effectively, each IP core must be exercised duly with the core vendor’s set of established test patterns. In case of VLSI systems, due to higher storage requirements for fault-free responses, the traditional test processes become quite expensive. Alternate approaches are pursued in order to reduce the test data volume or the amount of storage required.

A design methodology called BIST (Built-in-Self-Testing) [1] - [3] is capable of providing solutions to numerous problems faced in testing digital systems. In order to test a SOC, the test patterns are initially generated and stored in an exclusive computer. The increase in the different types of SOCs has increased the requirement for the numbers of test patterns and also the frequent downloading of these test patterns into an ATE (Automatic Test Equipment). The size of these test patterns can be quite large that it may require a lot of time for downloading an ATE. However, the data memory, input-output channel capacity, and speed of traditional ATEs are limited. These machines are also quite expensive. Because of this, newly developed compression techniques are expected to decrease testing time and storage capacity.

The emergence of new test vector compression techniques [4] [5] and data compression in SOC techniques (SOC containing an embedded processor core) [6] [7] has been recently reported. Embedded processor has significantly increased Soc design flexibility, lengthened SOC product lifetime, and reduced design errors by permitting the devices to adapt to evolving standards and by allowing the addition of extra features over time [8] . Therefore, the compression technique must not only be efficient enough to decrease the test data volume, but also effective enough in its decompression. Various techniques have been proposed in the literature for compressing test data and their decompression. The Test sets are compressed using the selective Huffman coding is presented in [9] assuming full scan circuits and allowing reduction of hardware overhead of Huffman FSM. The Test data is encoded by using nine-types of codeword, Nine-Coded Compression based on fixed to variable coding scheme. The drawback of the method is the increased length of symbol. Other methods are presented based on Frequency-Directed Runlength (FDR) [10] , Golomb Codes, Variable-input Huffman coding (VIHC), Lempel-Ziv-Welch (LZW) Coding [12] , Associative Coder of Buynovsky (ACB) [11] , Run Length Coding (RLC), Burrow-Wheeler Transform (BWT) [14] , Variable to Variable Huffman code and Tunstall coding. Compression techniques are proposed in order to reduce test data volume. In [10] , the test vectors are compressed as difference vectors T_diff from Original Test vectors T_D and this leads to the reduction of testing time and smaller test sets.

In this paper, a new technique has been presented for efficient implementation of test data compression and decompression for system-on-a-chip designs. This paper introduces a new class of variable length compression codes that are designed using the split-options along with identification bits of string of test data.

Test vector generation program was employed to obtain a set of test vectors to provide 100% fault coverage, MINTEST. The percentage of data compression is computed based on

The experimental results are shown in Tables 4-6 and Figures 3-5.

Table 4 and Table 5 show compression results obtained from ISCAS 85, ISCAS 89 combinational and sequential benchmark circuits. The scan size is also considered for combinational and sequential circuits and compression achieved is 80%. The column 4 illustrates the original size of test vectors and consequently remaining column shows the compression achieved for split options with various combinational and sequential circuits,

which is extended up to a value of 7.

Finally, Figure 3 and Figure 4 graphically shows the test vector compression results for several ISCAS 85 and ISCAS 89 benchmark circuits using SDV coding for various values of B. The graphical diagram shows that the overall average percentage for both combinational and sequential circuits is 80. Table 6 describes the overall compression percentage and time taken to compress the test data under the proposed scheme. Figure 5 shows graphically the time taken to compress the test data in seconds for combinational and sequential circuits.

Table 7 shows the compression results obtained from ISCAS 85 and ISCAS 89 benchmark circuits with comparison of other compression techniques. The Highest compression is obtained compared to Huffman coding, Lempel-Ziv-Welch (LZW) Coding, Associative Coder of Buynovsky (ACB), Burrow-Wheeler Transformation (BWT) presented in Table 7. From the proposed technique, data compression is achieved mainly due to SDV technique in successive test vectors. Figure 6 shows the comparative results of various techniques along with proposed technique. From the comparative experimental results, the developed compression strategy provides better compression results than other various compression methods.

Since test data compression is the most important technique it must be lossless and effective. The compression

method herein is based on a Split-Data Variable length (SDV) coding technique that targets to split-off the bits to achieve compression. The technique SDV reduces the test vector sequences, and results in a higher compression ratio. The compression process is done before downloading the test vectors into the on-chip memory. The method proposed helps in reducing the test data and testing time. Further this method proposed herein is completely lossless because of its higher compression ratio.

J. Robert Theivadas,V. Ranganathan,J. Raja Paul Perinbam, (2016) System-on-Chip Test Data Compression Based on Split-Data Variable Length (SDV) Code. Circuits and Systems,07,1213-1223. doi: 10.4236/cs.2016.78105