MultiSupply Voltage Domain (MSVD) technique is an effective method to reduce both dynamic and leakage powers in modern system-on-chips. It consists of partitioning the design into separate voltage domains. Based on timing requirements, each module can be operated at a proper power supply voltage level [1] - [3] . Time critical domains run at higher power supply voltage (VDDH) to maximize performance, while noncritical domains run at lower power supply voltage (VDDL), to reduce static and dynamic power without impacting on the overall circuit performance. In MSVD system, level shifters (LSs) are required on the boundaries between the circuit subsections operating at different power supply voltages to convert signals from the VDDL to the VDDH voltage level.

Multithreshold CMOS technique is mainly used to optimize the delay and power of the circuit. It consists of two levels of threshold voltage such as low threshold voltage and high threshold voltage. Low threshold voltage is used to increase the speed and reduce the clock period. High threshold voltage is used to reduce the static power leakage. Sleep transistors are series to the pull-up and/or the pull-down of the logic gates, and turn them off when the circuit is idle, thereby decreasing the leakage component due to sub-threshold currents. When an nMOS sleep transistor is used on the pull-down path, a SLEEP signal controls its active/standby mode (i.e., SLEEP during standby and SLEEP during active mode) [4] - [6] . In the standby mode, the sleep transistor is off, thus disconnecting its insertion point, called virtual ground, from the physical ground. In active mode, the gated circuit operates normally, but it incurs delay degradation due to the series resistance of the sleep transistor.

The common LS is the differential cascade voltage switch (DCVS) circuit that is typically used for changing signals between the two different above-threshold voltage domains. Drawback of the DCVS-LS is the conflict between the pull-up and pull-down networks which becomes severe when input signals are in the subthreshold range, thus making the conventional sizing methods impractical to get a properly functioning circuit. To address this problem, in order to improve the performance several conventional DCVS circuits have been proposed. The four-stage cascaded DCVS circuit was designed for robust level up-conversion from the subthreshold region. But it introduced large power penalties to the intermediate power supplies and also limited speed performance [7] - [9] .

A two-stage LS was proposed, the first stage exploits a DCVS circuit with an always-on diode-connected nMOS transistor on the top; whereas, the second one is a conventional DCVS stage that achieves rail to rail swing. It avoids intermediate power lines, but again it is not enough to reach high-speed performances. The LS was designed by two pMOS current limiters to reduce the half-latch pull-up strength within the conventional DCVS structure. This circuit is able to convert subthreshold input signals and it requires reasonably sized pull- down transistors. Also this LS is relatively slow and energy-hungry. A circuit based on current mirrors has been designed for better speed performance, but the current mirror output floats when the input voltage signal is high [10] - [12] . This causes a detrimental effect on subthreshold leakage of the output buffer.

Recently, LS was designed, it is suitable for fast and wide range voltage conversion from the subthreshold domain to above-threshold domain, but it has high power consumption. A new low-power LS is designed to improve the speed and reduce the power by using multithreshold CMOS technique and sleep transistor.

This paper is organized as follows. Firstly, the related work is briefly explained in Section 2; next, the proposed methodology is described in Section 3. Then, the results and discussion are described in Section 4. Finally, the content is concluded in Section 5.

The Level shifter in the system is mainly used for fast and wide range voltage conversion in Multi Supply Voltage Domain [7] . Multi Threshold CMOS (MTCMOS) technique is used in the architecture of level shifter circuit. These circuit which gives robust voltage shifting from the deep sub-threshold to the above-threshold domain, while demonstrating fast response and low energy consumption [13] - [15] .

The LS circuit is shown in Figure 1 is designed by using the multi-threshold CMOS design technique along with novel topological strategies. The circuit consists of an input inverter, a main voltage conversion stage and an output inverting buffer. The input inverter (MP₁/MN₁) is designed using low threshold voltage (lvt) transistors. To have higher strength of the pull-down network, also MN2 and MN3 are lvt transistors. Then, two lvt pMOS devices (MP₂ and MP₃) are added to both the branches of the circuit.

These devices limit the cross-bar current that is the current flowing in the pull-up network and opposing to the discharge of NH (or NL) node at the beginning of their high to low transition. To further facilitate the high to low transition at the nodes NH and NL, MP₄ and MP₅ are high threshold voltage (hvt) transistors. This choice also reduces leakage current flowing through the pull-up networks when MP₄ or MP₅ are turned off. However, using hvt, pMOS transistors has the counter effect of slowing the low to high transition of the nodes NH and NL. Therefore, to reduce the switching delay, a pull-up network able to self-adapt its strength to the actually occurring desirable transition [16] - [18] .

This behavior was obtained by introducing the parallel connected hvt devices MP₆-MP₁₀ and MP₇-MP₁₁,

with MP₆ and MP₇ being diode connected transistors. The two variable virtual power supplies on the two branches of the circuits are V_NHH and V_NLL. Therefore, the strength of pull-up networks is adapted to the next output switching transition. Assuming that the output Z is initially low (high), the pull-up network of the left branch is weakened (strengthened) and that of the right branch is strengthened (weakened), thus speeding-up a low-to-high (high-to-low) output transition.

The introduction of hvt MP₁₀ and MP₁₁ devices controlled by NH and NL voltages. To assure a rail-to-rail conversion, an output inverting buffer is connected to the node NH. This inverter uses a standard threshold voltage (svt) nMOS (MN₄) device and two stacked hvt pMOS transistors (MP₈ and MP₉). The used pull-up configuration allows static current when NH is high to be significantly reduced. In such a condition, the MP₉ device has the effect of maintaining the source node of MP₈ below V_DDH. As the source terminal of MP₈ results to be at lower voltage than its bulk node, the MP₈ threshold voltage increases. The source-gate voltage of MP₈ is also reduced, thus further reducing static current in the above referred condition. These LS is suitable for robust logic voltage shifting from near/sub-threshold to above threshold domain has been presented. This circuit exploits proper design strategies to increase the operating speed while maintaining low energy consumption and large voltage conversion range [19] [20] .

Table 1 represents the sizing of transistor in existing system. Proper transistor sizing can be achieved by changing the aspect ratio of the transistors, i.e. width and length of the transistors. MN₁ to MN₂ denotes the nMOS transistors and MP₁ to MP₁₁ denotes the pMOS transistors.

The proposed low power level shifter is mainly used for power reduction and wide range voltage conversion in MultiSupply Voltage Domain. Novel level shifter architecture is combined with Multi Threshold CMOS (MTCMOS) technique can be achieved by proper sizing of transistors and sleep transistor. This circuit provides robust voltage shifting from the deep sub-threshold to the above-threshold domain with low power consumption.

The proposed level shifter is suitable for robust logic voltage shifting from near/subthreshold to above-threshold domain. The proposed circuit exploits proper design strategies to maintain very low energy consumption and large voltage conversion range. Sleep transistor technique is used which is able to further reduce the total leakage power from the circuit to the ground by breaking the physical connection to the ground. And also low

power consumption can be achieved by proper sizing of transistor. The proposed design reliably converts 100 mV input voltage into 1 V output voltage. The simulation results demonstrate that the new LS shows power of 2.56 nW compared to existing system power of 5.66 nW.

The proposed level shifter is used in many applications. In future, the proposed level shifter is implemented in flip-flop circuit for further reducing the power and achieves the voltage conversion from subthreshold to above- threshold.

The authors are grateful to the Dean of Anna University, Regional Office-Madurai and management and principal of K.L.N. College of Engineering for providing all facilities for their research work.

Raveendran Arun Prasath,Parasuraman Ganesh Kumar, (2016) Design of Low Power Level Shifter Circuit with Sleep Transistor Using MultiSupply Voltage Scheme. Circuits and Systems,07,1132-1139. doi: 10.4236/cs.2016.77097