From olden days, several inverters have been used due to different applications. Voltage Source inverters have wide applications which include drive control strategy, STATCOM, HVDC transmission, and more important is that the interfacing of renewable energy resources. In Power Quality improvement voltage source topology was widely used in SVC’s, UPQC’s, etc. due fast and dynamic response characteristics [8] [11] . Moreover, in UPQC, voltage source converters certain unbalance DC link voltage due fast short duration operation. The advantages of voltage source inverter are:

-Produce pure sinusoidal current waveforms by reducing unwanted harmonics.

-Lessens the overvoltage produce by refection on extended cable.

-Ripple is two times normal the switching frequency in the first set.

Figure 2 shows the Voltage source inverter (VSI) topology as an active filter .This topology permits switches to tolerate higher DC voltage input on the sites that the switches will not elevate the level of withstanding voltage [6] [10] .

Conventional control topology for parallel active filter controlled by the hysteresis scheme in voltage source inverter is shown in Figure 3 and its modeling is defined as follows.

Three phase voltage is given as:

where V is the line voltage measured across three phases a, b, c correspondingly. Hysteresis Current Controller is helping to identify the mitigated reference current. Then the inside and outside of hysteresis comparator are stated as:

Effective switching pulses are used to generate three different voltages on the AC side of the active filter. Upper and lower voltages existing in the negative and positive phase voltages of the inverter acted as an active filter. In optimistic side voltage produced on two levels, 0 and , and the destructive side voltage level produced are, and 0. A Voltage is produced in order to increase the level of compensating voltage, whereas the level of voltage on high side 0 is to reduce compensated voltage. Thus, for every half cycle in switching high and low level voltage was selected alternately in order to select compensated current for each thyristor [6] [12] - [14] .

where, if; or 0 if and x = a, b, c.

Logic control is used in controlling the both Active Power Filters for providing gate signals. The Difference between the injected and reference current gives a reference modulation waveform. The inverter control is determined by two strategies [12] [13] . Determination of intermediate signals V_im1 and V_im2:

- If E_c ³ 1 at that time V_im1 = 1

- If E_c ³ 1 at that time V_im1 = 0

- If E_c ³ 1 at that time V_im2 = 0

- If E_c ³ 1 at that time V_im2 = 1

where and are midway signal, is the modulation reference error signal.

The main aim of this control approach is to compensate current harmonics which usually based upon the synchronous reference frame detection method [3] . The control approach is based upon the load currents i_la, i_lb, i_lc, are converted into 3 phase (a,b,c) reference frame and then to two phase () stationary reference frame currents and using: [15] - [20] .

By means of phase locked loop (PLL), that make possible for generations of and from phase voltages such as, V_as, V_bs, and V_cs.

The and currents obtained from (d-q) reference frame are written as:

The i_d and i_q current are transformed into DC components and using a low pass filter harmonic components are obtained:

The equation for the reference current -ref and -ref as,

The abc reference frame is given as:

Finally, the compensation currents are obtained as;

In order to mitigate, initially the inverter losses are reduced and then normalize the DC link voltages using a PI voltage controller [21] . The loop produces an equivalent current given as:

For generating reference frame for series active filter depending upon the PQ theory, we assume phase voltages are symmetric and distorted: [3] [15] [17] [19] . The Figure 5 shows the series active filter control for generating the filter reference voltage at the time of distortion occurred in the supply voltage.

The U_n and are rms voltages and primary phase angle, n is the harmonic order. When n = 1, it means that the fundamental 3-phasesupply voltage;

Equation (10) is converted into reference frame:

The fundamental 3-phase current is framed as:

Equation (10) is transformed to () reference frame:

The DC components are obtained by passing P and Q in low pass filter (LPF), then

From the above equation the transformation is made as:

The DC mechanisms of p and q as:

The fundamental reference frame is given as:

The three-phase fundamental voltages are given as:

Here both shunt and series power filters are put into operation at different time instants. Considering nonlinear load for simulation source parameters considered are as follows. Input source voltages: V_a = 230 V, V_b = 230 V, V_c = 230 V. The load element and filters with VSC has been built using MATLAB /SIMULINK. The following observations are drawn from the simulation outcomes. The control algorithm provides reactive and harmonic power compensation.

Here balanced source voltage is considered and after compensation balanced source current is prescribed in following results. Figure 6 shows the three phase balanced source voltages which is being supplied to the system. Figure 7 depicts the three phase error voltage which is generated due to the load connected to UPQC.

At time instant for t = 0 to 0.05 sec system is working without any issues, which does not require any compensation and after t = 0.05 voltage dip is introduced, in this time period series filter comes into operation for compensating voltage harmonics. The voltage dip occurs till 0.1 sec, the system is again at normal working condition. Then a short time interruption is led which occur from t = 0.14 to 0.15 sec, following the interruption

voltage swell is hosted from t = 0.15 to 0.18 sec at that time shunt filter comes into operation for compensating harmonics due rise in voltage, then the system voltage come back to its normal working condition.

In Figure 8 voltage from t = 0 to 0.05 sec remain zero because of normal operation at time 0.05 sec voltage dip arise the reference voltage generator generates required amount of voltage to compensate dip which occur till 0.1 sec. At t = 0.14 sec there is a small interruption for 0.01 sec so reference voltage generator generates the necessary voltage to maintain source voltage as normal. At t = 0.15 sec there is 10% rise (V_s = 253 volt) in voltage till 0.18 sec. So reference voltage generator generates the required voltage in the opposite direction for mitigation.

Three phase actual (generated) error voltage which is being added to the system error voltage to obtain the compensated source voltage of 230 volts for an entire operating period, it is shown in Figure 9.

In Figure 8 and Figure 9 there are few overshoots at t = 0.5 secs, t = 0.1 secs, t = 0.14 ecs, t = 0.18 secs respectively. This overshoots are due to sudden injection of reference components (voltage/Current) while mitigating the pq issues like sag, swell and etc., in the respective fault points. The duration of this overshoot exist for few milli or micro seconds. These overshoots can be reduced by selecting suitable values of L and C of the active filters and its controllers in the proposed UPQC.

The supply current before compensation is non-sinusoidal due to the non-linear load connected to the system which is shown in Figure 10.

The generated reference current for compensation using hysteresis controller is exactly follows the reference filter current shown in Figure 11. It is generated by the synchronous reference current generator and is presented in Figure 12.

The generated reference current Figure 12 is injected into the source current at the load terminal (normally at the point of common coupling). It results sinusoidal current which is in phase with the source voltage shown in Figure 13. Hence the Total Harmonic Distortion (THD) is improved from 30.59% to 0.83%.

There is a small disturbance in time t = 0.05, 0.1, 0.14 and 0.15 respectively, which is due the operation of controller during the mitigation process of dip, interruption and swell.

Considering same simulation load parameters, but having unbalanced sources are as follows. Input source voltages: V_a = 230 V, V_b = 220 V, V_c = 230 V.

From t = 0.05 sec voltage dip is introduced, in this time period series filter comes into operation for compensating voltage harmonics. Then a short time interruption is led which occur from t = 0.14 to 0.15 sec, following the interruption voltage swell is hosted from t = 0.15 to 0.18 sec at that time shunt filter comes into operation for compensating harmonics due rise in voltage, then the system voltage come back to its normal working condition.

Here unbalanced source voltage is considered and after compensation balanced source current is prescribed in following results. Figure 14 shows the three phase unbalanced source voltages which are supplied to the system. Figure 15 and Figure 16 are the error voltage and its corresponding actual error voltage generated by using proposed control strategy.

Three phase actual (generated) error voltage shown in Figure 16, which is being added to the system error voltage to obtain the compensated source voltage of 230 volts for an entire operating period, it is shown in Figure 17.

Figure 18 shows the supply current before compensation and which is in non-sinusoidal due to non-linear

load connected to the system. The actual filter current generated by the synchronous reference current generator using hysteresis controller for the connected non-linear load is shown in Figure 20. It is exactly matched with source reference current shown in Figure 19.

Figure 20 shows compensated source voltage in phase with the source current which is obtained by injection of generating reference current to source current at load terminal. There is a small ripple in the compensated current waveform shown in Figure 21 is due to the injection of reference current and voltages at various points at the point of common coupling. By designing a suitable filter component, the short duration ripples are quenched quickly.

The above tasks are analyzed by using MATLAB Simulink for two different operating conditions such a balanced and unbalanced source voltage conditions. The amount of harmonic distortion reduction is up to the benchmark level and its results are tabulated in Table 1. Table 1 shows the numerical statistics of the THD values under before and after compensation of the current in the proposed system. The THD improvement in both operating conditions is more satisfactory with the standard of IEEE value.