HBT base SiGe film deposition uses ASM E2000plus reduced pressure chemical vapor deposition (RPCVD) equipment. Unlike substrate cleaning of conventional epitaxy, the wafers were dipped into dilute HF solution after being cleaned by standard RCA cleaning in order for H atoms to passivate wafer surface completely, then were dehydrated, and finally were put into RPCVD machine. This treatment is aimed at eliminating the need of high-temperature treatment to prevent MOS structure, formed through preceding steps, from changing. Only 2-minutes baking at 900˚C would obtain a clean, oxygen free, epitaxial growth surface. To further reduce thermal budget, SiH₂Cl₂ was replaced by SiH₄ as Si source. GeH₄ is used as Ge source, dopant source uses B₂H₆, and deposition temperature was 650˚C. SiGe stack layers for Ge-graded profile were composed of 5 steps. At a constant SiH₄ flow of 20 sccm, Ge-content graded downward by gradually reducing GeH₄ flow from 60 sccm to 0.

Figure 1 is the designed, RPCVD-deposited HBT multi-layer structure. Layer 1 is 15 nm thick, 15% Ge, uniform profile, undoped SiGe. Layer 2 is 22 nm thick SiGe with Ge-graded profile (15% to 0%) at B dopant concentration of 2e19 cm⁻³. Layer 3 is 40nm thick Si cap at B dopant concentration of 5e18 cm⁻³. Figure 2 is SIMS-measured thicknesses, Ge and B profiles, tallying with what were designed. Figure 3 is SiGe base rocking curve measured by high-resolution X-ray diffractometer (XRD). Figure 4 is reciprocal space map measured by XRD. From Figure 3 and Figure 4, it can be concluded that the quality of SiGe stack layers was good, that SiGe stack layers were fully strained, and that there was no relaxation in SiGe stack layers.

As strain exists in SiGe, SiGe is restricted by temperature throughout SiGe processing. To reduce affection of thermal technology, HBT production in 0.35 µm SiGe BiCMOS process technology was after MOS formation, avoiding thermal processes such as source/drain implantation annealing, gate oxidation. HBT device used mainly deep trench isolation technology in order to reduce the parasitic effect and favor f_T improvement; outer base region used metal silicide (TiSi₂) in order to reduce R_b and make for decreasing noise figure; selectively injected collector (SIC) process was used to decrease R_e, thus suppressing bulk injection effect and enhancing β and f_T; dual poly (outer base rejoin, emitter rejion) process was used to reduce C_jc and C_je, to reduce RC delay, and also to favor increasing f_T.

HBT device performance parameters, including the DC and AC parameters, were tested. Figure 5 is HBT I-V output characteristic curve, Figure 6 is HBT Gummel curve, Figure 7 is HBT Beta curve, and Figure 8 is HBT frequency characteristics (f_T = 67 GHz). Current gain of HBT device is 150, and cutoff frequency of HBT device is 67 GHz.