The different circuit and logic styles result in different gate and diffusion capacitance of the transistors in a combinational logic circuit [6] . Some of the circuit styles can substantially reduced the physical capacitance and is good for low-power operation. Figure 3 represents the power-delay products of an 8-bit adder relationship between that was implemented in 2 μm CMOS technology with different circuit styles and the corresponding propagation delays.

As shown in Figure 2, the adder that was implemented by using complementary pass transistor logic (CPL) is about twice as fast as the conventional static CMOS. This is due to that CPL improves the performance of the circuit with a lower input capacitance and reduced voltage swing. Moreover, a CPL logic circuit consumes less power than a static CMOS one, for instance, the power saving for a CPL adder is about 30% compared to a conventional static CMOS adder [7] . This improvement is mainly due to the reduction in capacitance. The performance of a full adder implemented with different circuit styles, such as conventional CMOS, transmission gate CMOS. Power dissipation of the circuit dramatically on the delay circuit styles to reveals this comparison. The compared results indicate that the CPL-TG provides the lowest power delay product, and the LCPL2 has the second lowest power delay product. Both of them are the best suited for low-power high-performance applications such as adders and multipliers.

The capacitive load that originates from transistor capacitance and interconnect wiring can be reduced by optimizing transistor sizes whenever possible and reasonable. In general, increasing the transistor sizes results in a large (dis)charging current and simultaneously increases the parasitic capacitance. On the other hand, reducing the transistor sizes will result in decreasing input capacitance that may be the load capacitance for other gates and lowering the speed of the circuit. Thus, the objective of transistor sizing is to obtain the minimum power dissipation under given performance requirements. In order to explain how to make transistor sizing, let us consider a static inverter driving a load capacitance being composed of an intrinsic (diffusion) and an extrinsic (wiring and fan out) capacitances. When the total load capacitance to the gate output is dominated by the diffusion capacitance, the smallest possible sizes of the transistors should be used for obtaining the lowest power consumption. Otherwise, if the load capacitance is dominated by the extrinsic component [8] .

C) Switching Activity Reduction

The dynamic power consumption of a circuit is strongly related to the switching activity of the circuit [8] . At the circuit level, one main consideration for low-power designs is the choice of the static or dynamic logic styles. The dynamic logic gates are clocked, and undergo the pre-charge and evaluation phases, which are suitable for high-speed applications for the expense of high power dissipation. Whereas the static CMOS is the best choice for low-power high-speed implementation of dedicated circuit applications like multipliers .The switching activity can be reduced by many means such as reordering input signals, no bus-sharing technique, and minimizing the glitching activity of the static circuits etc.

Glitches, or dynamic hazards, are unwanted signal transitions which occur before the signal settles to its intended value. Glitches can be generated and propagated in both data path and control parts of the circuits. The simulation result from the circuit simulator (Specter) was obtained under the different conditions. The spurious transitions consume extra power compared to the glitch-free scenarios. The number of spurious transitions in a circuit depends on the logic depth, input patterns, and intermediate carry signal states etc.

The glitching activity in static circuit designs can be minimized by selecting structures with balanced signal paths and reduced logic depth. The tree structures can be applied to implement a circuit with both of the balanced signal paths and less logic depth, while the chain structures are quite the contrary. A good example in Figure 4 illustrates the choice of the tree or chain structures [5] . The second adder computes twice and the third adder computes three times per cycle due to the finite propagation delay through the previous adders. By contrast, the logic depth in the tree case has been reduced from three to two and the signal paths are more balanced. Thus, the switched capacitance (effective capacitance) for the chained case is a factor of 1.5 larger than in the tree [8] [9] .

Another possible approach to eliminate the spurious transitions is to use dynamic logic circuits instead of static logic, since any node in dynamic logic circuits can only undergo at most one transition per clock cycle.

D) Reduction Technique for Leakage Power

The number of typical reduction for leakage techniques fall in two categories, either leveraging the stack effect or increasing the transistor threshold voltage. Forcing transistors into stacks is not a scalable solution and its implementation becomes very complicated for large designs. There are three main reasons for minimizing leakage current. They are (i) source/drain junction leakage current which is due the junction acts as an diode in reverse bias when the transistor is in sleep mode. i.e. in OFF. (ii) Is gate tunneling leakage current which flows through the oxide to substrate? If the gate oxide is thin, then the current increases exponentially. And the third one is (iii) sub threshold leakage current, which is a current from source to drain. It is diffusion current built by minority carriers in the channel in the MOS devices [9] .

As technology scales into the deep-submicron (DSM) regime, standby sub threshold leakage power increases exponentially with the reduction of the supply voltage vdd and the threshold voltage vth. For many event driven applications, such as mobile devices where circuits spend most of their time in an idle state with no computation, stand by leakage power is especially detrimental on overall power dissipation [10] . Multi-Threshold CMOS (MTCMOS) is an effective circuit-level methodology that provides high performance in the active mode and saves leakage power during the standby mode. The basic principle of the MTCMOS technique is to use low vth transistors to design the logic gates where the switching speed is essential [11] , while the high vth transistors (also called sleep transistors) (Figure 5) are used to effectively isolate the logic gates in standby state and limit the leakage dissipation. The sleep transistors are turned on when the circuit is active and turned off when the circuit is idle. By cutting off the power source, this technique can reduce leakage power effectively.