Increasing demand of bandwidth and support of multimedia traffic in mobile/wireless environment has developed the need of further improvement of wireless communication system performance. Turbo codes exhibit near Shannon-capacity performance and thus are specified in third generation cellular standards particularly in UMTS and cdma2000 [1]. The performance of iterative turbo decoder approaches near Shannon-capacity with increased number of iterations, which introduces computational delay in the system resulting in reduced throughput. The throughput performance can be improved by employing adaptive turbo decoder that adapts the decoding algorithm on the basis of prevailing channel conditions. The focus of this paper is on developing adaptive turbo decoder for reducing computational delay and thus improving throughput of the system [2]. There exists many advanced turbo decoding algorithms providing different combinations of performance and complexity. Here we consider log-MAP, max-log-MAP, constantlog-MAP and linear-log-MAP algorithms [3].

This paper evaluates above decoding schemes and proposes an adaptive turbo decoding architecture, and named it as generalized turbo decoder. The generalized decoder analyzes the channel conditions and selects appropriate decoding algorithm accordingly. For favorable channel conditions fast converging and least complex algorithm is selected, such as max-log-MAP. And, for poor channel conditions, the algorithm offering best BER performance but slow converging and complex algorithm is considered, such as log-MAP algorithm. Meticulous selection of decoding algorithms results in reduced computational delay, and thus improving throughput, which are complemented by simulation results. The proposed decoder architecture has the same architecture as proposed in [3] with an additional block of channel estimator to estimate the channel statistics, depending upon the channel conditions. The proposed decoder selects the appropriate decoding algorithm and optimizes the decoding performance, on the basis of channel conditions. The simulation results show that the proposed decoder architecture achieves the desired BER performance with reduced number of iterations and thus converges faster. The paper also contributes some critical implementation issues and discusses, in particular the computation of the max* operator. Simple, but effective, solutions for complexity problems are proposed and illustrated through simulations results. However, in the description of the algorithm, we have not provided the details of Viterbi algorithm [4] with the assumption that it is known to the reader. The remainder of this paper is organized as follows: Section 2 provides an overview of the UMTS turbo encoder and Section 3 discusses the channel model and how to normalize the inputs to the decoder. The next three sections describe the decoder, with Section 4 describing the algorithm, Section 5 discussing the system model, and Section 6 describing max* operator implementation of the MAP algorithm. The performance evaluation of the proposed generalized turbo decoding and log-MAP algorithm for fading channel is carried out in Section 7. Finally, Section 8 concludes the paper.

As shown in Figure 1, the UMTS turbo encoder is composed of two constraint length 4 Recursive Systematic Convolutional (RSC) encoders concatenated in parallel [5,6]. Feedback of shift register output to input of encoder effect the behavior of error pattern. The feedforward generator is 15 and the feedback Generator is 13, both in octal. The number of data bits at the input of the turbo encoder is K. Data is encoded by the first (i.e., upper) encoder in its natural order and by the second (i.e., lower) encoder after being interleaved. At first, the two switches are in the up position. Data is feed into the interleaver in a row wise fashion (with the first data bit placed in the upper-left position of the matrix) followed by intrarow or interrow permutations on each the matrix depending on the block length [7]. After the intrarow and interrow permutations, data is read from the interleaver in a column wise fashion. The data bits are transmitted together with the parity bits generated by the two encoders. Thus, the overall code rate of the encoder is, not including the tail bits (discussed below). The first 3 output bits of the encoder are in the form: where is the th systematic (i.e., data) bit, is the parity output from the upper (un interleaved) encoder, and is the parity output from the lower (interleaved) encoder. After the data bits have been encoded, the trellises of both encoders are forced back to the all-zeros state by the proper selection of tail bits. The tail bits of an RSC will depend on the state of the encoder. The tail bits are generated for each encoder by throwing the two switches into the down position, thus causing the inputs to the two

encoders to be indicated by the dotted lines. The tail bits are then transmitted at the end of the encoded frame according to

where and represents the tail bits of the upper and lower encoder, and represents the parity bit of upper and lower encoder. Thus, when tail bits are taken into account, the number of coded bits is, and the code rate is.

BPSK modulation is assumed, along with either an AWGN or flat-fading channel. The output of the receiver’s matched filter is, where for the systematic bits, for the upper encoder’s parity bits, for the lower encoder’s parity bits, is the channel gain (for AWGN and is a Rayleigh random variable for Rayleigh flat-fading), n_k is Gaussian noise with variance

,

is the energy per code bit, is the energy per data bit, and is the one-sided noise spectral density. The input to the decoder is in the form

By applying Bayes rule and assuming that

where is the conditional probability density function (pdf) of given, which is Gaussian with mean and variance. Substituting the expression for the Gaussian pdf and simplifying yields

Thus, the matched filter coefficients must be scaled by a factor before being sent to the decoder. The notation denotes the received LLR corresponding to systematic bit, denotes the received LLR for the upper parity bit, and denotes the received LLR corresponding to the lower parity bit.

The architecture of the decoder is as shown in Figure 2.

Decoding will be done in an iterative manner, because of the feedback [8]. Each full iteration consists of two half iterations, one for each constituent RSC code. The timing of the decoder is such that RSC decode#1 operates during the first half-iteration, and RSC decoder#2 operates during the second half iteration.

The value, , is the extrinsic information produced by decoder#2 and introduced to the input of decoder#1. Before to the first iteration, is initialized to all zeros. After each complete iteration, the values of will be updated to reflect beliefs regarding the data propagated from decoder#2 back to decoder#1. is not defined for so it will be taken as 0. The output of RSC decoder#1 is the LLR of that is obtained by

Similarly for decoder#2

Once the iterations have been completed, a hard bit decision is taken using, where when and when.

Here one modification is that a channel estimator as in [9], is attached with the decoder that will estimate channel condition through received pilot symbols [10,11]. Two RSC decoders choose the decoding process that will depend on the channel condition. Since for lower log-map algorithm is used where high does not require it, so here we can use some linear approximation that will reduce complexity and increase throughput. The flowchart of decoding operation is given below:

Flow chart for proposed turbo decoding process.

Each of the two RSC decoders in Figure 2 operates by sweeping through the code trellis twice, once in each of the forward and reverse directions. Each sweep uses a modified version of the Viterbi algorithm to compute partial path metrics, where the modifications is that the ACS operations are replaced with the max* operator. Here we use different algorithm technique for different channel condition.

The RSC decoders in Figure 2 are each executed using a version of the classic MAP algorithm [12] implemented in the log-domain [13]. The algorithm is based on the Viterbi algorithm [4] with two key modifications: First, the trellis must be swept through not only in the forward direction but also in there verse direction, and second, the add-compare-select(ACS) operation of the Viterbi algorithm is replaced with the Jacobi logarithm, also known as the max* operator [14] here we consider four versions of the algorithm: log-MAP, max-log-MAP, constant-logMAP, and linear-log-MAP. The only difference among these algorithms is the manner in which the max* operation is performed.

If we decode the same received frame by all four algorithm. The bit error rate (BER) is shown for the bit UMTS turbo code in Figure 4 for 10 iteration.  If the simulations were run to, an error floor would begin to appear. The beginning of a floor can be seen in the simulation of the bit code in AWGN channel [14]. Similarly, it can be seen in Rayleigh fading channel for higher. In the error floor region, all four algorithms will perform roughly the same. It can be seen in Figure 4 that the algorithms are beginning to converge as the BER curves begin to flare into a floor. Thus, while the choice of algorithm has

acritical influence on performance at low signal-to-noise ratio.

The choice becomes irrelevant at high SNR. This suggests that in a software implementation [18], perhaps the algorithm choice should be made adaptive (e.g., choose linear-log-MAP at low SNR and max-log-MAP at high SNR).

Regarding to above discussion we could make a generalized decoding process for AWGN channel which can decode as a log-MAP decoder when, linear-log-MAP decoder when, constant-log-MAP decoder when, maxlog-MAP decoder when. The proposed concept of generalization can be used in Rayleigh fading channel for higher.

The simulations were run on a PC with a 2.13-GHz Intel Core-i3 CPU and the 64 bit Windows 7 operating system for and 10 decoder iteration. From the Figures 5 and 6 it is clear that BER performance little bit reduced in case of generalized decoding scheme but the overall throughput for generalized decoding is seven times greater than log-map decoding. Analysis also confirms that the log-MAP decoding algorithm is the least-efficient algorithm as compared to max-log-MAP algorithm in terms of processing power and computational delay; it is mainly due to complex process of calculating correction function for log-MAP decoder.

The other three algorithms are of similar complexities, with max-log-MAP shows minimal computational delay resulting in highest throughput per iteration. A comparison of the constant-log-MAP and linear-logMAP algorithms shows that there is the tradeoff between them in terms of complexity and performance. However, the linear-logMAP algorithm offers slightly better BER performance at the cost of slight reduction in overall throughput.

This type of generalised decoding algorithm can be use in software implimention for fixed number of iterations. From Figures 7 and 8 clearly shows that the as the number of iterations increases the BER decreases.

In this paper, we propose a simple but effective adaptation of generalized turbo decoder. The proposed algorithm is characterized and evaluated through extensive simulation, showing that it optimizes the decoding performance with faster convergence. The simulation results shows that the adaptation of log-MAP based turbo decoding schemes offer better performance in terms of enhanced overall throughput with reduced complexity in comparison to the log-MAP algorithm. This has been achieved at the expense of only a modest increase in BER.