<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE article  PUBLIC "-//NLM//DTD Journal Publishing DTD v3.0 20080202//EN" "http://dtd.nlm.nih.gov/publishing/3.0/journalpublishing3.dtd"><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" dtd-version="3.0" xml:lang="en" article-type="research article"><front><journal-meta><journal-id journal-id-type="publisher-id">WJNST</journal-id><journal-title-group><journal-title>World Journal of Nuclear Science and Technology</journal-title></journal-title-group><issn pub-type="epub">2161-6795</issn><publisher><publisher-name>Scientific Research Publishing</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.4236/wjnst.2012.24027</article-id><article-id pub-id-type="publisher-id">WJNST-23799</article-id><article-categories><subj-group subj-group-type="heading"><subject>Articles</subject></subj-group><subj-group subj-group-type="Discipline-v2"><subject>Engineering</subject><subject> Physics&amp;Mathematics</subject></subj-group></article-categories><title-group><article-title>
 
 
  New Method for Diagnostics of Ion Implantation Induced Charge Carrier Traps in Micro- and Nanoelectronic Devices
 
</article-title></title-group><contrib-group><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>ukhtar</surname><given-names>Ahmed Rana</given-names></name><xref ref-type="aff" rid="aff1"><sub>1</sub></xref><xref ref-type="corresp" rid="cor1"><sup>*</sup></xref></contrib></contrib-group><aff id="aff1"><label>1</label><addr-line>Physics Department, International Islamic University, Kashmir Highways, Islamabad, Pakistan</addr-line></aff><author-notes><corresp id="cor1">* E-mail:<email>rana@alumni.nus.edu.sg</email></corresp></author-notes><pub-date pub-type="epub"><day>31</day><month>10</month><year>2012</year></pub-date><volume>02</volume><issue>04</issue><fpage>174</fpage><lpage>180</lpage><history><date date-type="received"><day>August</day>	<month>14,</month>	<year>2012</year></date><date date-type="rev-recd"><day>September</day>	<month>15,</month>	<year>2012</year>	</date><date date-type="accepted"><day>September</day>	<month>25,</month>	<year>2012</year></date></history><permissions><copyright-statement>&#169; Copyright  2014 by authors and Scientific Research Publishing Inc. </copyright-statement><copyright-year>2014</copyright-year><license><license-p>This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/</license-p></license></permissions><abstract><p>
 
 
  An important problem of defect charging in electron-hole plasma in a semiconductor electronic device is investigated using the analogy of dust charging in dusty plasmas. This investigation yielded physical picture of the problem along with the mathematical model. Charging and discharging mechanism of charge carrier traps in a semiconductor elec-tronic device is also given. Potential applications of the study in semiconductor device technology are discussed. It would be interesting to find out how dust acoustic waves in electron-hole plasma in micro and nanoelectronic devices can be useful in finding out charge carrier trap properties of impurities or defects which serve as dust particles in elec-tron-hole (e-h) plasma. A new method based on an established technique “deep level transient spectroscopy” (DLTS) is described here suggesting the determination of properties of charge carrier traps in present and future semiconductor devices by measuring the frequency of dust acoustic waves (DAW). Relationship between frequency of DAW and properties of traps is described mathematically proposing the basis of a technique, called here, dust mode frequency deep level transient spectroscopy (DMF-DLTS).
 
</p></abstract><kwd-group><kwd>Semiconductors; Ion Implantation; Defects</kwd><kwd> Dust Acoustic Waves; Deep Level Transient Spectroscopy; Electron-Hole Plasma; Nanoelectronics</kwd></kwd-group></article-meta></front><body><sec id="s1"><title>1. Introduction</title><p>During the fabrication, defect or particulate contamination of microelectronic device structures is a serious concern. It can be due to unwanted growth on growth reactor walls or impurities in supply of atomic species in the reactor. Extended defect structures are also formed in different semiconductors used in electronic devices during ion implantation. Extended structures in ion implanted Sb doped Ge (Ge: Sb) form extended defect structures which show high thermal stability and also transform to other defect phases rather than repair. These defects have fatal effects on transport of charge carriers in semiconductor thin films used in electronic devices, which makes knowledge about them important [1-4]. Due to limitation of carrier mobility in Si, Ge has emerged as a key ingredient material for fabrication of a new generation of ultrafast devices in the regime of tens of gigahertz. Ion implantation can be used to write a network of devices on a semiconductor wafer due to possibility of controlled implantation beam size and energy, and masking of the target wafer.</p><p>Elemental implantation defects, especially charge carrier traps, and their electronic implications in Ge and similar materials have not been understood with sufficient details, so a comprehensive understanding of properties of defects (vacancies and self-interstitials) in Ge and related materials, and their interactions with impurity atoms is still required [4-7]. These elemental defects join impurities in implanted/doped semiconductors to form defect clusters which act as charge carrier traps. A generalized model for charging and discharging of defects in semiconductor electronic devices is presented here along with its perspective applications.</p></sec><sec id="s2"><title>2. A Model of Defect/Impurity Charging</title><sec id="s2_1"><title>2.1. Physical Picture</title><p>In a perfect crystal of, say, Ge or Si, all the atoms are at their lattice sites and do not have ability to trap additional charge carriers. If impurities are introduced in a perfect crystal, they get ability to trap charge carriers. It may be noted that self interstitial and vacancies are also defects and can trap charge carriers. In real crystalline structure grown for use in devices, contain a variety of defects and sometimes form defect clusters. These clusters are normally composed of vacancy-dopant or interstitial-dopant clusters. These extended clusters can trap a considerable fraction of electrons or holes present in the active volume of a device.</p><p>It is thought that these types of extended defect clusters are present in N-type Ge and prevent the feasibility of high speed electronic devices. Depending upon crystal and dopant, preset defect clusters can trap electrons or holes depending on the coulomb potential around defect, impurities or a defect cluster. Electron-hole plasmas are found in electronic devices crystals exposed to optical excitations etc. Defect clusters are exposed to electron and hole currents due to which they are charged. Defect charging in semiconductors is quite complex. After charging processes end, charged defects start discharging naturally. Charging/discharging of defect clusters in semiconductor devices are important and affect performance of devices. Charging and discharging of defects can be used for characterization of charge carrier traps in micro and nanoelectronic devices. Behaviour of deep level traps, which forms the basis for DLTS technique, is described by a schematic in <xref ref-type="fig" rid="fig1">Figure 1</xref> showing electron and hole traps in a semiconductor. Capture &amp; emission by deep-level traps in a semiconductor. DLTS makes use of the measurement of the depletion region of a simple semiconductor electronic device, normally, a Schottky diode. In such a measurement, the regular reverse polarization of the diode is modified by the probing voltage pulse, resulting in the flow of carriers from the bulk to the measurement region, charging the defects or traps. After the pulse ends, thermal emission of carriers from the traps produces the capacitance transient in the device, called the DLTS signal.</p></sec><sec id="s2_2"><title>2.2. Mathematical Model</title><p>Suppose an electron-hole plasma is generated in an electronic device with electron density as n<sub>e</sub> and hole density n<sub>h</sub> For simplicity, we assume here extended defect clusters capable of trapping a considerable number of electrons. We consider a case of net electron trapping or negatively charged defects in a semiconductor device. The model situation resembles the typical case of ion implanted Ge:Sb. For the simplicity, we assume that at the time of generation of electron-hole plasma, n<sub>e</sub> – n<sub>h</sub><sub>. </sub>In implanted Ge:Sb, highly stable vacancy-antimony-Ge clusters (<img src="10-1090079\f994586f-d0c3-4ca5-9395-49c4203ce48e.jpg" />) are present which are thought to be electron traps in this n-type Ge. These extended defect clusters get charged like dust particles and grains in electron-ion plasma. Let the density of defect cluster or dust grain in e-h plasma, generated in the above mentioned device, is n<sub>d</sub>.</p><p>We further assume here that densities of electrons and holes are below the limit at which inter particle distance becomes lower than de Broglie wavelength of any specific specie which assures that that the case e-h plasma being discussed here is of classical nature. If we take charge of electron as –e, hole as +e and defect or dust grain s – Z<sub>d</sub>&#183;e, the well-known condition of charge neutrality can be written as below:</p><disp-formula id="scirp.23799-formula16422"><label>(1)</label><graphic position="anchor" xlink:href="10-1090079\4268af9d-70f9-4ff2-b398-6ee5a5c04b3b.jpg"  xlink:type="simple"/></disp-formula><p>Using simple algebra,</p><disp-formula id="scirp.23799-formula16423"><label>(2)</label><graphic position="anchor" xlink:href="10-1090079\aad66d03-d34e-4f29-b8b6-993d1f633d9b.jpg"  xlink:type="simple"/></disp-formula><p>For any practical device, defect grain density is much lower than densities of electrons and holes, so the number</p><p><img src="10-1090079\74e7b254-65da-423d-90c0-c7381c2efc25.jpg" /></p><p>which is the case of isolated dust or defect grains [8-11]. It may also be noted that in present devices defect grains can be only up to a few nanometer size. Maximum charge on defect depends upon defect structure and its size. A isolated defect or dust grain in e-h plasma attains a floating potential <img src="10-1090079\8b3ce94d-6912-4bab-8e1c-ba941ff428ec.jpg" /> which is determined by electron repulsion and hole collection in case of net negative charging of defects. The electron current responsible for depositing electrons on the defect is given by,</p><disp-formula id="scirp.23799-formula16424"><label>(3)</label><graphic position="anchor" xlink:href="10-1090079\ac0e8fb9-0ff1-4046-80bd-5213d44bff86.jpg"  xlink:type="simple"/></disp-formula><p>where m<sub>e</sub> and T<sub>e</sub> are electron effective mass and temperature, and <img src="10-1090079\098b1842-f021-4516-abae-767fb765c7fe.jpg" /> is the radius of the equivalent sphere of defect grain. The hole current compensating electron charging of a defect is given by,</p><disp-formula id="scirp.23799-formula16425"><label>(4)</label><graphic position="anchor" xlink:href="10-1090079\119a8274-db13-4b92-8cf4-a7364486c469.jpg"  xlink:type="simple"/></disp-formula><p>where m<sub>h</sub> and T<sub>h</sub> are hole effective mass and temperature. For further details of equations (3), (4), please see Refs. [8-12]. The charging equation of a negatively charged grain can be written as below, [8-10].<sup></sup></p><disp-formula id="scirp.23799-formula16426"><label>(5)</label><graphic position="anchor" xlink:href="10-1090079\3b6d7270-ed2e-402d-bdfb-ac8aa775534f.jpg"  xlink:type="simple"/></disp-formula><p><sup>&#160;</sup></p><p>Case of hole or positive charging of defects can be described using a simple analogy and comparison between electrons and holes.</p></sec><sec id="s2_3"><title>2.3. Mechanism of Charging and Discharging of Electron Traps in an Electronic Device</title><p>Electron traps are centers in a semiconductor capable of trapping electrons with a certain binding energy. Traps cause power dissipation and reduce conductivity of the device. When electrons and holes are present in the form of a plasma in an electronic device, dust or defect grains are exposed to both electron (T<sub>e</sub>) and hole (T<sub>h</sub>) currents. These currents simultaneously charge and discharge defect grains. When e-h plasma is first generated (t = 0) in an electronic device, a charging transient is produced after which charging and discharging perturbation continues until the device operation ends (end of e-h pair generation). After this, a discharging transient is produced in which electrons are released due to thermal agitation and thermally generated holes. UV light can also produce discharging through photoelectron emission.</p></sec></sec><sec id="s3"><title>3. New Method for the Diagnostics of Charge Carrier Traps in a Microand a Nanoelectronic Device</title><p>The frequency ω of dust acoustic mode in electron ion plasma, with dust charged as negative, is given by [8-10],</p><disp-formula id="scirp.23799-formula16427"><label>(6)</label><graphic position="anchor" xlink:href="10-1090079\2f7ec929-c0c2-480f-8001-b5afcaf19822.jpg"  xlink:type="simple"/></disp-formula><p>where k is the wavenumber, k<sub>B</sub> is the Boltzman constan, Z<sub>d</sub> is charge on the dust, n<sub>d</sub><sub>0</sub> and n<sub>i</sub><sub>0</sub> are, respectively, equilibrium dust and ion densities, m<sub>i</sub> and m<sub>d</sub> are, respectively, ion and dust masses, T<sub>e</sub> and T<sub>i</sub> are electron and ion temperatures respectively and e is the electronic charge. With take the case of semiconductor device working at room temperature and having low electron and hole densities (due to low doping level) so that plasma behavior is classical. With charge traps or dust in the device, the above equation the following form by replacing ion parameters with hole parameters,</p><disp-formula id="scirp.23799-formula16428"><label>(7)</label><graphic position="anchor" xlink:href="10-1090079\a3ffa152-141b-4a38-ab35-1a799a73c665.jpg"  xlink:type="simple"/></disp-formula><p>Now, m<sub>h</sub> and n<sub>h</sub><sub>0</sub> are, respectively, hole mass and equilibrium density. Dust particles in e-h plasma are impurities or defect clusters which can be positively charged, negatively charged or neutral. Dust particles in e-h plasma can have a range of mass and mobility coefficient as they can be free or loosely or strongly bound to the host lattice structure. So, dust model in e-h plasma in electronic devices can be of quite complex nature.</p><p>Here, following questions about e-h-dust plasma in semiconductor devices are investigated. What can be the nature of dust modes in e-h-dust plasma in semiconductor devices? Can these dust modes be useful in diagnostics of present or future micro or nanoelectronic devices? What can be the practical method of utilizing dust modes in diagnostics of semiconductor devices?</p><p>Dust particles (impurities or defects) in a semiconductor device act as electron or hole traps depending upon its electronic structure. If a pulse of electrons or holes is injected into a semiconductor device, as in a charge carrier trap characterization technique DLTS [13-15], these dust particles will be charged with electrons are holes.&#160; After the charge carrier feeding pulse ends, charged defects or dust particles will start discharging and it will continue until dust particles or defects reach their equilibrium charge. Dust mode frequency will also change as dust charge changes with time. This changing mode frequency with time is given by the following,</p><disp-formula id="scirp.23799-formula16429"><label>(8)</label><graphic position="anchor" xlink:href="10-1090079\67229232-f280-4be0-9382-91b92eb2fb94.jpg"  xlink:type="simple"/></disp-formula><p>In DLTS technique, the device is biased at a reverse bias V<sub>R</sub> at which the bias is pulsed by a trap filling pulse V<sub>P</sub> for a time t<sub>p</sub>. Filled defect states start emptying, when bias returns back to V<sub>R</sub>, and that results in a capacitance transient. Filling pulse is applied in a series and the varying capacitance of the diode <img src="10-1090079\cb4f8880-16d0-4644-a523-4136ade77706.jpg" /> is given by [<xref ref-type="bibr" rid="scirp.23799-ref16">16</xref>],</p><disp-formula id="scirp.23799-formula16430"><label>(9)</label><graphic position="anchor" xlink:href="10-1090079\32fae0cb-c4f6-43d7-a593-718a01323478.jpg"  xlink:type="simple"/></disp-formula><p>where <img src="10-1090079\7a1924a2-ca17-42ca-bab0-e97097ef99d0.jpg" /> is the equilibrium capacitance value at reverse voltage, <img src="10-1090079\53a175d4-f5f7-4e5b-8267-c57226b273f4.jpg" />is the lowering of <img src="10-1090079\d36f699d-c3db-488a-91b6-eadec89502eb.jpg" /> at t = 0 and e<sub>p</sub> is the hole emission coefficient. The above equation will be valid for electron traps with e<sub>p</sub> replaced with e<sub>n</sub> (the electron emission coefficient) and <img src="10-1090079\0e60764c-f5c7-4273-b2a5-3a4ed2001d3f.jpg" /> is the rise of <img src="10-1090079\8a028349-dc4e-4890-9e21-993cb3c6530c.jpg" /> at t = 0. DLTS spectrum is generated by applying a sine-function correlation with period P to <img src="10-1090079\74670809-e5f0-4c74-8d9e-a91e35d212d2.jpg" /> as,</p><disp-formula id="scirp.23799-formula16431"><label>(10)</label><graphic position="anchor" xlink:href="10-1090079\12832db2-43ad-416e-8751-248799d8139c.jpg"  xlink:type="simple"/></disp-formula><p>The above procedure is applied to determine fundamental Fourier component of the transient,<img src="10-1090079\0f1f46f7-aa50-48a8-84dc-4d33f457bfd1.jpg" />. For exponential transients, the period P, the emission coefficient e<sub>p</sub> and T<sub>max</sub> for which <img src="10-1090079\b6813bba-9f50-458b-936f-8cbcc87aa49c.jpg" /> shows a maximum, are related as [<xref ref-type="bibr" rid="scirp.23799-ref17">17</xref>]</p><disp-formula id="scirp.23799-formula16432"><label>(11)</label><graphic position="anchor" xlink:href="10-1090079\a2e54387-34cd-4b49-808a-0b87e9bb28f5.jpg"  xlink:type="simple"/></disp-formula><p>By choosing different appropriate values of period P, corresponding values of e<sub>p</sub> and T<sub>max</sub> can be determined for a specific transient <img src="10-1090079\a8eaa6be-6c3c-4e5a-932c-1aca8e0653ff.jpg" /> corresponding to a particular hole trap.</p><p>As clear from Equation (3), the frequency of dust would depend on varying charge Z<sub>d</sub> of dust particles in the same way as <img src="10-1090079\a4fbdd12-a033-49ff-a3f7-fa549359e531.jpg" /> during dust or trap discharge after the application of the filling pulse. So, dust mode frequency transient <img src="10-1090079\c4d9821f-0014-472f-8d75-202481456513.jpg" /> for the same hole trap as in Equation (4), an analogue to capacitance transient<img src="10-1090079\4ca7cb06-22a9-439a-ba3a-1bfafd58ad38.jpg" />, can be defined as,</p><disp-formula id="scirp.23799-formula16433"><label>(12)</label><graphic position="anchor" xlink:href="10-1090079\4b3dad79-ae79-448a-b59e-99c7dbbd2ffd.jpg"  xlink:type="simple"/></disp-formula><p>where <img src="10-1090079\fe5a1f13-4915-4575-bd64-a417bfd46b15.jpg" /> and <img src="10-1090079\24c7d79c-81e7-4a9e-9fbe-30f977c1d4f8.jpg" /> are, respectively, equilibrium dust mode frequency and full magnitude of the frequency transient at t = 0. In the same way as in Equation (5), dust mode frequency DLTS or DMF-DLTS signal, <img src="10-1090079\b31e715c-df76-4167-b774-0cc89f187555.jpg" />, can be generated by applying the correlation sine-function as in Equation (5),</p><disp-formula id="scirp.23799-formula16434"><label>(13)</label><graphic position="anchor" xlink:href="10-1090079\145a6a5e-6c84-4fdc-8911-b847cde7dd7c.jpg"  xlink:type="simple"/></disp-formula><p>DMF-DLTS will show a set of peaks of <img src="10-1090079\001a48ab-a5ea-4a21-93a9-c29cda7ea3a2.jpg" /> signal, each corresponding to a particular dust specie. This spectrum of peaks will be similar to a DLTS spectrum (<xref ref-type="fig" rid="fig2">Figure 2</xref>) with different DLTS peaks, with peak parameters carrying finger prints of dust species. Once dust mode frequency <img src="10-1090079\b96f1486-04d9-49fd-8c8c-05d1b5b4cfa6.jpg" /> and change <img src="10-1090079\05636002-283a-4693-861b-ba8a5a0e9a1b.jpg" /> are measured, further details of experimental and analysis aspects of implementation of this new DLTS can be seen by a selected studies available in the common literature [13-19].</p></sec><sec id="s4"><title>4. Potential Applications and Discussion</title><p>The present investigation provides the essential information for understanding charging/discharging of defects in semiconductor electronic devices using transient and steady state conditions of operation. It is well known that switching on and off of a range of electronic devices affects their life. Charging and discharging currents produced, respectively, in switching on and off of an electronic devices affect its quality life.</p><p>Deep level transient spectroscopy [13-15] makes use of charging and discharging capacitance transients for characterization of charge carrier traps in a semiconductor electronic device. According to this study small scale charging and discharging perturbations continue even during steady state operation of devices. These perturbations would have higher magnitude and intensity if an electronic devices operation different operational stages. These perturbations produce a fluctuating filed in the device. Fluctuating fields can have more deleterious effects on the operating device, especially if the fluctuation frequency is high.</p><p>Here, we classify defects in a semiconductor electronic device into three classes which are electronically inactive defects, electronically static defects and electronically dynamic defects. Electronically dynamic defects continue producing charging and discharging transients in an operating device and are most undesirable. Electronically inactive defects only decrease active volume of the device and have minimum undesirable effects whereas electronically static defects trap charge carriers but do not produce negligible charging and discharging transients after getting charged at start up of the device. The work presented here in conjunction with the fundamental plasma work [20,21] may lead to applications in the field of Nanotechnology [22,23] and nuclear instruments and methods [24-27].</p><p><xref ref-type="fig" rid="fig3">Figure 3</xref> is a pictorial view of findings of the paper. Physical significance of charge carrier traps in a semiconductor is shown graphically at the right bottom of the figure. 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