<?xml version="1.0" encoding="UTF-8"?><!DOCTYPE article  PUBLIC "-//NLM//DTD Journal Publishing DTD v3.0 20080202//EN" "http://dtd.nlm.nih.gov/publishing/3.0/journalpublishing3.dtd"><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" dtd-version="3.0" xml:lang="en" article-type="research article"><front><journal-meta><journal-id journal-id-type="publisher-id">JSIP</journal-id><journal-title-group><journal-title>Journal of Signal and Information Processing</journal-title></journal-title-group><issn pub-type="epub">2159-4465</issn><publisher><publisher-name>Scientific Research Publishing</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.4236/jsip.2012.33050</article-id><article-id pub-id-type="publisher-id">JSIP-22136</article-id><article-categories><subj-group subj-group-type="heading"><subject>Articles</subject></subj-group><subj-group subj-group-type="Discipline-v2"><subject>Computer Science&amp;Communications</subject></subj-group></article-categories><title-group><article-title>
 
 
  A Storage Architecture for High Speed Signal Processing: Embedding RAID 0 on FPGA
 
</article-title></title-group><contrib-group><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>ingxiao</surname><given-names>Sun</given-names></name><xref ref-type="aff" rid="aff1"><sup>1</sup></xref><xref ref-type="corresp" rid="cor1"><sup>*</sup></xref></contrib><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Qiongzhi</surname><given-names>Wu</given-names></name><xref ref-type="aff" rid="aff1"><sup>1</sup></xref></contrib><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Zhaojian</surname><given-names>Jin</given-names></name><xref ref-type="aff" rid="aff1"><sup>1</sup></xref></contrib></contrib-group><aff id="aff1"><addr-line>Beijing Institute of Technology</addr-line></aff><author-notes><corresp id="cor1">* E-mail:<email>sunningxiao@sina.com(IS)</email>;</corresp></author-notes><pub-date pub-type="epub"><day>31</day><month>08</month><year>2012</year></pub-date><volume>03</volume><issue>03</issue><fpage>382</fpage><lpage>386</lpage><history><date date-type="received"><day>April</day>	<month>20th,</month>	<year>2012</year></date><date date-type="rev-recd"><day>May</day>	<month>25th,</month>	<year>2012</year>	</date><date date-type="accepted"><day>June</day>	<month>10th,</month>	<year>2012</year></date></history><permissions><copyright-statement>&#169; Copyright  2014 by authors and Scientific Research Publishing Inc. </copyright-statement><copyright-year>2014</copyright-year><license><license-p>This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/</license-p></license></permissions><abstract><p>
 
 
  The article proposes a new architecture based on RAID 0 tech in computer science for signal processing field to store high speed data. It is composed of SSD driven by FPGA, called SSD-based RAID on FPGA. This new architecture features high storage rate, mass capacity and small volume, and it is an efficient solution to store high speed data. The article describes the construction of SRF in details, and shows the test result of a demo system based on the architecture.
 
</p></abstract><kwd-group><kwd>RAID on FPGA; SSD; High Speed Data Storage</kwd></kwd-group></article-meta></front><body><sec id="s1"><title>1. Introduction</title><p>In signal processing field, the system designer has been greatly forced to choose between real-time processing and the storage capacity of the acquisition signal. In the past, the latter always limits the maximum count rates supported without data loss. Systems which could perform both functions at the same time were usually too costly and complex. To solve these problems the first target is to find a sort of the storage medium [<xref ref-type="bibr" rid="scirp.22136-ref1">1</xref>].</p><p>Now, with recent advancements in the computer industry, the cost of NAND flash memory becomes lower and the density of NAND flash memory grows larger, the mass-production of solid state drives (SSD) based on NAND flash memory was launched on a full scale [<xref ref-type="bibr" rid="scirp.22136-ref2">2</xref>]. SSD is strong in shock and its I/O performance is better comparing with the conventional hard disk drive (HHD).</p><p>Though the storage rate of SSD increases remarkably compared to HHD, SSD alone is hard to meet most requirements of data acquisition and storage system [3,4]. Therefore, RAID 0 tech in computer science is introduced, and we propose an architecture of RAID, which is based on SSD and driven by FPGA, called SSD-based RAID on FPGA (short for SRF), which features mass capacity, high rate and small volume. In addition, in order to save costs, the architecture of SRF is designed to be adjustable in storage rate and capacity.</p></sec><sec id="s2"><title>2. Architecture of SSD-Based RAID on FPGA</title><p><xref ref-type="fig" rid="fig1">Figure 1</xref> depicts the architecture of the SSD-based RAID on FPGA.</p></sec></body><back><ref-list><title>References</title><ref id="scirp.22136-ref1"><label>1</label><mixed-citation publication-type="other" xlink:type="simple">K. Park, “Reliability and Performance Enhancement Technique for SSD Array Storage System Using RAID Mechanism,” The 9th International Symposium on Communications and Information Technology (ISCIT 2009), 28-30 September 2009, pp. 140-145.</mixed-citation></ref><ref id="scirp.22136-ref2"><label>2</label><mixed-citation publication-type="other" xlink:type="simple">W. F. Jones, “A Digital Architecture for Routinely Storing and Buffering the Entire 64-Bit Event Acquisition in Clinical Real-Time 3-D PET: Embedding a 400 Mbyte/ sec SATA RAID 0 Using a Set of Four Solid- Solid-State Drives,” 2008 IEEE Nuclear Science Symposium Conference, 19-25 October 2008, pp. 5036-5040.  
doi:10.1109/NSSMIC.2008.4774371</mixed-citation></ref><ref id="scirp.22136-ref3"><label>3</label><mixed-citation publication-type="other" xlink:type="simple">J. Ren, “I-CASH: Intelligently Coupled Array of SSD and HDD,” The 17th International Symposium on High Performance Computer Architecture (HPCA), 12-16 February 2011, pp. 278-289.</mixed-citation></ref><ref id="scirp.22136-ref4"><label>4</label><mixed-citation publication-type="other" xlink:type="simple">W. Wu, “Implementing a Serial ATA Controller base on FPGA,” Computational Intelligence and Design (ISCID 09), Vol. 1, 12-14 December 2009, pp. 467-470.</mixed-citation></ref><ref id="scirp.22136-ref5"><label>5</label><mixed-citation publication-type="other" xlink:type="simple">S. S. Rizvi, “Data Storage Framework on Flash Memory Based SSD RAID 0 for Performance Oriented Applications,” The 2nd International Conference on Computer and Automation Engineering (ICCAE), Vol. 1, 26-28 February 2010, pp. 126-128.</mixed-citation></ref><ref id="scirp.22136-ref6"><label>6</label><mixed-citation publication-type="other" xlink:type="simple">K. R. Dandekar, H. Ling and G. H. Xu, “Smart Antenna Array Calibration Procedure including Amplitude and Phase Mismatch and Mutual Coupling Effects,” IEEE Conference on Personal Wireless Communications (PWC), Vol. 12, 2000, pp. 293-297.</mixed-citation></ref><ref id="scirp.22136-ref7"><label>7</label><mixed-citation publication-type="other" xlink:type="simple">Serial ATA Working Group, “Serial ATA High Speed Serialized AT Attachment Rev 1.0a,” Serial ATA Working Group, 2002, pp. 117-123.</mixed-citation></ref></ref-list></back></article>