The recent progress of process technology has caused various fluctuation problems in device characteristics due to transistor area reduction. The threshold voltage (Vth) fluctuation caused by dopant fluctuation strongly influences device characteristics [1,2]. Generally, this dopant induced Vth fluctuation is random and obeys a normal distribution.

The stability of SRAM cells is greatly affected by Vth fluctuation, because SRAM cells are usually designed using minimum design rules. Vth fluctuation degrades both the read and the write operation stabilities. It is said that the read operation is usually more critical than the write operation under Vth fluctuation. However, the write operation is also affected by a large Vth fluctuation. In addition, a recent paper indicates that write operation failure is more dominant than read operation failure under low supply voltage conditions [3]. Therefore, an accurate evaluation of write operation stability is as important as an evaluation of read operation stability.

Conventionally, the Write Noise Margin (WNM), based on the “butterfly curve”, is used as a metric of write operation stability [4]. Since the write operation is strongly affected by the Vth of the SRAM cell access transistors, the conventional WNM is also expected to be sensitive to Vth variation of the SRAM cell access transistors. However, the WNM is not sensitive to Vth variation when the WNM is large. In addition, the WNM does not obey a normal distribution. Takeda et al. described these problems and maintained the importance of a normal distribution of the WNM [5]. They proposed a new write margin definition which is sensitive to Vth variation of the access transistors and follows a normal distribution. Recently, several new definitions have been proposed [6-9]. If the write margin obeys the normal distribution, the write margin distribution can be easily estimated by a small number of samples [5]. This drastically improves development efficiency, especially when combined with the maximum likelihood method.

In this paper, we propose an accelerated evaluation method for the SRAM cell write margin using the conventional butterfly curve based WNM definition. The WNM is measured at a lower word line voltage than the power supply voltage VDD and calibrated to the WNM of the VDD word line voltage. In the proposed method, the write margin obeys the normal distribution even under the conventional WNM definition.

In Section 2, the reason why the conventional WNM does not obey the normal distribution is analyzed. In Section 3, an accelerated evaluation method for the SRAM cell write margin is proposed based on the analysis in Section 2. In Section 4, the proposed method is verified using the Monte Carlo simulation. Finally, Section 5 provides the conclusion.

A diagram of the SRAM write operation circuit is shown in Figure 1. Let us assume that the inverted data are written to the SRAM cell where “1” is stored on the internal node V1 and “0” on the V2. Then, the data “0” and “1” are given on bit lines BL and /BL, respectively, under the activated word line WL. If the voltages of nodes V1 and V2 are inverted, the write operation is successful. Hereupon, V1, V2, BL, /BL and WL represent the voltages.

The definition of the conventional Write Noise Margin (WNM) based on the butterfly curve is shown in Figure 2. We draw the DC transmission curves of inverter A (InvA in Figure 1) and inverter B (InvB in Figure 1) under WL = VDD, BL = 0 V and /BL = VDD. The VDD is the power supply voltage. The WNM is defined as the width of the smallest embedded square between the two DC transmission curves.

Generally, the write margin is a function of the threshold voltage Vth’s of the six transistors in a SRAM cell. If

the write margin is linear on the Vth’s, the write margin is expected to obey the normal distribution, allowing us to predict the write margin distribution accurately from a small number of samples. Furthermore, if the write margin distribution is the normal distribution, the write yield can also be easily estimated [10].

The dependence of the WNM on the Vth is examined using the SPICE simulation. The transistor parameter of 45-nm process technology [11] is used with the power supply voltage of VDD = 1.0 V. The threshold voltages are the typical values of Vthn = 0.404 V for the NMOS transistors and Vthp = –0.384 V for the PMOS transistors. The transistor sizes are L = 45 nm and W = 55 nm, 83 nm, and 55 nm with for the access, driver, and load transistors, respectively.

The simulation results are shown in Figure 3. We set ΔVth = 0, a typical threshold voltage. The WNM is not linear on the Vth of the access transistor N1. However, the WNM is almost linear on the other transistors. The nonlinearity on access transistor N1 causes the WNM to deviate from the normal distribution [10]. In the lower Vth region, the load transistor P1 determines WNM = 0, that is, the write limit. In the higher Vth region, the access transistor N1 determines the write limit. The slope of the WNM for the N1 changes significantly near ΔVth = 0.1 V. The WNM is completely linear for ΔVth > 0.1 V. We call this area the linear section of the WNM for the N1. WNM = 0 is on this straight line. When ΔVth < 0.1 V, the slope of the WNM is almost equal to 0. This means that the WNM is not sensitive to Vth variation of the N1 when the WNM is large. This is consistent with previous research [5]. The access transistors only affect the WNM in the case of a large Vth variation. In other words, the WNM distribution has a tail at the side of the small margin. A large number of samples is needed in order to estimate the distribution. If we estimate the distribution with a small number of samples, with many appearing around ΔVth = 0, the predicted distribution is very sharp. This results in an overestimation of ΔVth for WNM = 0, because the slope of the WNM is nearly equal to 0 around ΔVth = 0.

The reason why the WNM has different slopes around

ΔVth = 0.1 V can be explained by a change in the operation mode of the access transistors when the WNM is evaluated. The dependence of the V1 on the ΔVth of N1 in Figure 1 is examined using the SPICE simulation at V2 = 0 V. The results are shown, together with the WNM, in Figure 4. The dashed line, which is determined by the equation V1 = VDD-Vth, represents the boundary of the operation mode of the access transistor N1. In the region to the left of the dashed line, the N1 operates in the linear mode and to the right of the dashed line, it operates in the saturation mode. Therefore, the operation mode of the access transistor changes around the point where the V1 curve intersects with the dashed line. The changing point of the WNM slope, which is around ΔVth = 0.1 V, closely corresponds to the changing point of the operation mode of the access transistor. Thus, a change in the slope of the WNM is strongly related to a change in the operation mode of access transistor N1.

In the AC write operation of a SRAM cell, access transistor N1 is always in the saturation mode at the beginning of the write operation because the V1 is not lower than the WL. Write failure occurs when the N1 stays in the saturation mode during the write operation. Therefore, the write margin should be evaluated in the saturation mode of access transistor N1. Contrary to the actual AC write operation, the conventional WNM is

evaluated in the linear mode of the access transistor when the write margin is large. Using the conventional WNM definition, therefore, is not an effective way to evaluate the stability of a SRAM cell.

In this section, we propose an accelerated evaluation method for the SRAM cell write margin based on the conventional WNM definition. In the proposed method, the access transistor is forced to operate in the saturation mode by lowering the word line voltage from the VDD. The WNM is then measured under the lower word line voltage. The word line voltage is chosen from a range which causes the access transistor to operate in the saturation mode. The WNM at the word line voltage of the VDD is calibrated from the measured WNM at the lower word line voltage. This calibrated WNM is called the Accelerated WNM (AWNM).

First, we measure the dependence of the WNM on the word line voltage. The WNM given by the SPICE simulation is shown in Figure 5. The power supply voltage is VDD = 1.0 V. The solid line represents the simulation results. The WNM is linear for a word line voltage of less than 0.9 V, meaning that the access transistor N1 operates in the saturation mode in this range of word line voltages, the equivalent of a high ΔVth. The slope change of the WNM at the word line voltage of 0.9 V corresponds to a change in the operation mode of the access transistor N1 around the threshold voltage of ΔVth = 0.1 V in Figure 4. The operation mode of the N1 moves to the linear mode in WL > 0.9 V.

Although the accelerated evaluation method using a word line voltage below 0.9 V gives a good linearity for the WNM, the value of the WNM itself is small when compared to the WNM at WL = 1.0 V. This is because the WNM is evaluated at a lower word line voltage. Therefore, this value is calibrated to the WNM at WL = 1.0 V. The dashed line in Figure 5 represents the extrapolated line. The extrapolated value of the WNM us ing the straight line is 0.35 V, the WNM at WL = 1.0 V, which is the AWNM in the proposed method.

In the accelerated evaluation method, the AWNM at WL = 1.0 V, denoted as AWNM (WL_1.0), is obtained from the measured WNM at a low word line voltage, the WNM (WL_m), as:

where α is the slope of the WNM for the WL voltage in the linear section. This AWNM is considered to be the write margin corresponding to the AC write operation.

Figure 6 shows the dependence of the WNM on the ΔVth at the word line voltage of 0.8 V. A negative value is defined as the maximum length of an embedded square in the crossed curves, as shown in Figure 7. This means that the data are not inverted. In Figure 6, the slope changing point of the WNM for the N1 moves to the left when compared to the slope changing point under the word line voltage of 1.0 V (Figure 3). As a result, the measured samples around ΔVth = 0 V are in the linear section. In Figure 8, the dependence of the WNM and AWNM on the ΔVth’s is shown for access transistor N1 and load transistor P1. The solid lines are the AWNM and the dashed lines are the WNM. The extrapolated lines are drawn from the AWNMs around ΔVth = 0 V. The extrapolated line for access transistor N1 gives the correct write limit because the threshold voltage ΔVth at AWNM = 0 predicted by the extrapolated line is the same as the ΔVth at WNM = 0. This means that measured samples around ΔVth = 0 V for the N1 predict the