CSCircuits and Systems2153-1285Scientific Research Publishing10.4236/cs.2012.32022CS-18541ArticlesComputer Science&Communications Engineering Physics&Mathematics Optimizing the Stage Resolution of a 10-Bit, 50 Ms/Sec Pipelined A/D Converter & Its Impact on Speed, Power, Area, and Linearity eralaPrasad Rao1*KondepudiLal Kishore1Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Hyderabad, India* E-mail:prasadrao_hod@yahoo.co.in(EPR);190420120302166175December 14, 2011February 22, 2012 March 1, 2012© Copyright 2014 by authors and Scientific Research Publishing Inc. 2014This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/

At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.

Switched Capacitor Sample and Hold Circuit; 1.5 Bits/Stage; Linearity; Power; Redundancy; Folded Cascode Op-Amp1. Introduction

Although many Pipelined ADC architectures are discussed in literature, the number of bits/stage conversion was always a designer’s choice. Many designers preferred a stage resolution of 3 bits just to reduce the design complexity. This paper discusses the options of number of bits/stage conversion techniques in Pipelined ADCs and their effect on area, speed, power dissipation and linearity. The paper examines 1, 1.5, 2, 3, 4 and 5 bits/stage conversion to implement a 10-bit Pipelined ADC. In the analysis, all the basic blocks are assumed to be identical.

The rapid advancements in electronics has resulted in digital revolution with telephony switching systems in 1970’s and continued with digital audio in 1980’s and digital video in 1990’s. This is expected to prevail in the present multimedia era and even can influence in future systems. Since all electrical signals are analog in nature and since most signal processing is done in the digital domain therefore, A/D and D/A Converters have become a necessity. Flash ADC makes all bit decisions in a single go while successive approximation ADC makes single bit decision at a time. Flash ADCs are faster but area increases exponentially with bit length while successive approximation ADC is slow and occupies less area.

Between these two extremes many other architectures exist deciding a fixed number of bits at a time such as pipeline and multi step ADCs. They balance circuit complexity and speed. Figure 1 shows recently published high speed ADC architecture applications and resolution versus speed. In general, three architectures are suitable for three important areas of usage. For example, over sampling converter is used exclusively to achieve high resolution (greater than 12 bits at low frequencies). For medium speed with high resolution multi step and Pipeline ADCs are promising. At extremely high frequencies, flash ADCs survive but only at low resolution.

Figure 2 shows resolution versus speed depicting this trend. Most architectures known to date are not likely to achieve a resolution of 12 bits at over 100 MHz using even 180 nm to 90 nm technologies. However, two high speed architectures, namely multi step, pipelined and folding are potential architectures to challenge in times to come.

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