The rapid growth in semiconductor technologies through the use of deep submicron processes has led to the function sizes of MOS gadgets shrinking, thereby integrating extraordinarily complicated functionality on a single chip. In the ever-growing advertising demands of cellular hand-held gadgets used all over the world nowadays, battery-powered digital systems are the backbone. To maximize the battery life and the amazing computational capacity or storage potential of multimedia-supportable gadgets and battery-operated notebook computer systems, personal communication devices consisting of cellular telephones, pocket computers, PDAs, hearing aids, and implantable pacemakers or defibrillators need to be found with very low power requirements. The development and fast growth in the semiconductor era have reduced the feature sizes by contracting or shrinking the MOS transistors via the usage of deep submicron approaches or nanoscale approaches. In sleep mode, to reduce leakage, the device is turned off. This approach affords a massive reduction in leakage with a minimum effect on performance. It’s been shown that the energy gate technique makes use of high-voltage sleep transistors. With miniaturization and the growing trends and developments of the microelectronics era towards wireless communication, power dissipation and physical size have become very crucial design challenges. The power dissipation has not been completely removed, even with the scaling down of the supply voltage. The problem of heat removal and power dissipation is getting worse as the magnitude of power per unit area keeps increasing. The component failure rate approximately doubles for every 10˚C - 15˚C increase in the operating temperature of the portable devices. According to Moore’s law, the manufacturing of on-chip devices doubles every 18 months or almost two years. Minimizing power consumption and physical size has become an extremely challenging area of research. These techniques also suffer from turning-on latency. The latency affects the control of leakage power. The Basic Structure of the static CMOS Leakage Source is reported in Figure 1.

Figure 1. Basic structure of static CMOS leakage source.

The literature reports a large number of techniques for reducing power dissipation and leakage current in CMOS and VLSI circuits. As CMOS technology continues to scale into deep-submicron and nanometer regimes, reducing the supply voltage has become essential for minimizing dynamic power consumption. However, technologies scaling also leads to a significant increase in leakage current, making leakage power one of the major challenges in modern integrated circuit design. To overcome this issue, researchers have proposed numerous leakage reduction approaches, including advanced leakage reduction techniques, sub threshold leakage optimization in FinFET devices, leakage power modeling for deep-submicron technologies, and recent leakage suppression methods for power electronic converters such as three-level inverters [1]-[4]. Furthermore, power gating has emerged as an effective solution for ultra-low-power CMOS circuits, while transistor stacking, input vector control, and self-controllable voltage level techniques have been widely investigated to suppress standby leakage in digital circuits and SRAM cells [5]-[8]. Several studies have also focused on the analysis and characterization of leakage reduction methodologies, including body biasing, transistor stacking, and other device-level optimization techniques for deep-submicron CMOS technologies [9][10]. In addition, novel low-power sequential circuits, such as pulse-triggered D flip-flops, energy-efficient SRAM cells, hybrid full adders, and dynamic body-biasing-based logic circuits, have been proposed to achieve significant reductions in both leakage power and overall energy consumption [11]-[15]. Various circuit-level optimization methods, including transistor stack techniques, multi-threshold CMOS (MTCMOS), pass-transistor-based pull-up/pull-down insertion, and low-power clocking schemes, have further demonstrated substantial improvements in power efficiency [16][17]. Fundamental studies on modern VLSI devices have provided a comprehensive understanding of leakage current mechanisms and their impact on circuit performance [18]. Building upon these principles, several leakage control techniques, such as LECTOR (Leakage Control Transistor), Sleepy Keeper, Gated-VDD, SCCMOS (Super Cut-Off CMOS), and efficient transistor stack-based approaches, have been extensively explored for minimizing standby leakage without significantly affecting circuit performance [19]-[26]. Collectively, these studies demonstrate that a combination of device-level, circuit-level, and architectural optimization techniques is essential for achieving ultra-low-power and leakage-efficient CMOS circuit designs in advanced technology nodes.

To achieve low power through LSSR is formed by combining LECTOR technique and LSSR. It has the features of both approaches and thus is more beneficial than the previous work done. The circuit is proposed by introducing two gated leakage transistors between pull-up and pull-down networks with high threshold voltage, and then stack effect is added to pull-up and pull-down networks by dividing each transistor into half-size transistors.

CMOS simulation processes have been performed using HSPICE software in 32 nm, 45 nm, 90 nm, and 180 nm with model of Berkeley Predictive Technology Model parameters for the standard CMOS at room temperature with supply voltage 0.6 V - 1.0 V to estimate delay, static and dynamic power, and power consumption. Table 1 presents the simulated power dissipation and propagation delay of different circuits, and Table 2 yields the static and total power delay of NAND GATE, CMOS Inverter, FULL ADDER, LECTOR, and Stack Gates. In order to compare the proposed technique with the base case and other techniques: LECTOR and LECTOR Stack State Reduction for CMOS Inverter, AOI-OAI Circuits, NAND gate and 1-bit full adder circuits have been implemented. Simulation results for CMOS Inverter, AOI-OAI Circuits, NAND gate and 1-bit full adder circuit cases have been measured with random input vector values changing every clock cycle. According to simulation results represented in graphs and regarding the number of transistors used, a significant decrease in sub-threshold current, approximately 2 to 4 times in both NAND and Full Adder circuits, has been achieved, compared to traditional and other designs. There is an acceptable propagation delay compared to the base case concerning the high-resistance path LECTOR network and also a slight difference in dynamic power. Inputs of Full Adder have been adjusted so that they can change status in different input vector values or logic levels (0, 0), (0, 1). (1, 0), (1, 1). The outputs of circuits (sum, carry) without pass transistors have been shown according to inputs as Ain, Bin, and Cin, yielding the effect of using switching transistors, which has caused a considerable decrease in propagation delay. Through the simulation waveforms and the characteristics of LECTOR AOI resemble the base case. The LECTOR implementation involves the addition of two LCTs in each gate between the supply and ground path. For a particular MOS transistor, whenever the applied gate-to-source voltage is less than the threshold voltage of the transistor, there is no flow of current. Mathematically, when I_ds = 0 at V_gs < V_t. Tunneling through the gate oxide occurs because the thickness of the gate oxide layer is gradually reduced as technology is reduced to nanometers. The gate oxide tunneling current is caused by tunneling of electrons through an nMOS capacitor with a heavily doped n + polysilicon gate and a p-type substrate. Simulation for the 2-input NAND is performed by taking four different process parameters, viz. 32 nm, 45 nm, 65 nm. 90 nm and 180 nm. From the simulation, we analyze that as we scale down the technologies in the deep submicron regime, leakage current dominates. It is observed that when we move from 180 nm towards 45 nm, leakage current increases drastically up to 94.94% due to the reduction of the threshold voltage of CMOS transistor; as we scale down the channel length, leakage current increases. We observe that maximum leakage current flows at (1, 1) input vector combinations at 32 nm, 45 nm, 90 nm and 180 nm CMOS technology, respectively. All the simulations are performed using BPTM libraries in HSPICE simulator at 32 nm, 45 nm, 90 nm and 180 nm, with a load capacitance of 1 pF at 10 MHz frequency at supply voltages of 1.8 V, 1.5 V, 1.2 V, 1 V and 0.9 V. Metal-oxide-semiconductor field-effect transistor (MOSFET) channel length variation effect employing input-controlled stacking (MTCMOS) approach. The MOSFET’s channel length affects the overall performance of the logic circuits. The channel length varies from 22 nm to 88 nm to obtain the channel length variation. Further, the channel lengths of NMOS and PMOS devices are considered equal. The widths of the NMOS and PMOS devices are maintained at 2 and 4 times the channel length, respectively. The supply voltage is a key factor that affects power dissipation and propagation delay. The effect of supply voltage variation on the proposed MTCMOS and LSSR approaches is investigated by varying the supply voltage from 0.6 to 1.0 V. The effect of supply voltage variation on input-controlled stacking (LECTOR and LSSR approaches) is investigated. There are 4 possible combinations for 2-input NAND; hence, the average of the four power dissipations gives the leakage power. In the case of 4-input AOI, power dissipations corresponding to all the 16 combinations are averaged. For a full adder, the average of 8 power dissipations is the static power dissipated. LECTOR uses two LCTs, which are self-controlled transistors. LECTOR and LSSR present efficient reduction in leakage power, like other leakage reduction techniques, such as sleepy stack, sleepy keeper, etc., along with the advantage of not affecting the dynamic power. Since this technique does not require any additional control and monitoring circuitry and also in this technique, the exact logic state is in each case, the leakage power is measured by exciting both the circuits (Conventional and LECTOR) with the same set of input vectors. Static or leakage power dissipation is leakage currents, reverse-biased currents and substrate injection currents, which flow through the transistors in their steady states. Threshold voltages, to achieve high performance and low dynamic power dissipation, become more significant with the deep-submicron and nanometer technologies and thus it becomes a great challenge to overcome the problem of leakage power. International Technology Roadmap for Semiconductors indicates that leakage power consumption dominates the total chip power consumption as technology advances to the nanoscale. In future mobile computing, multimedia-supporting devices and mobile communication applications are fully restricted by their large supply voltage and battery life; battery life is a major concern. The proposed techniques can be implemented in CMOS Circuits as well as low-power VLSI circuits and save the power consumption of the chip, which leads to increased battery life. The simulated power dissipation and propagation delay of various circuits for CMOS Process 45 nm Technology are reported in Table 3 and the simulated power dissipation and propagation delay of various circuits for CMOS Process 45 nm Technology are reported in Table 4. Dynamic power, total power and delay of NAND, CMOS inverter, FULL ADDER and their LECTOR and Stack gates are reported in Table 5.

Table 3. Simulated power dissipation and propagation delay of different circuits for CMOS process 45 nm technology.

Table 4. Simulated power dissipation and propagation delay of different circuits for CMOS process 32 nm technology.

Table 5. Dynamic power, total power and delay of NAND, CMOS inverter FULL ADDER and their LECTOR and stack gates.

Table 6. W/L ratio for NMOS.

W/L ratios for NMOS and PMOS transistors are reported in Table 6 and Table 7. Total power, dynamic power and leakage power vs operating voltage is reported in Figure 17 and normalized delay vs V_dd is shown in Figure 18.

Table 7. W/L ratio for PMOS.

Figure 17. Presents total power, dynamic power and leakage power vs operating voltage.

Figure 18. Normalized delay vs V_dd.

In this paper, the LSSR technique is presented as a more efficient method for NAND, CMOS circuits, and full adder circuits in 32 nm technology with a 0.6 V power supply. Based on the results, LSP, compared to other approaches such as MTCMOS, LECTOR and Forced STACK, had better operation in reducing leakage power. Therefore, sub-threshold current has been reduced by 89% in relation to the base case, 76% compared to LECTOR, and 23% compared to Sleepy Keeper. Also, propagation delay has been improved, so that this technique is suitable for high-speed circuits in DSM regime. In the future, the LSP technique as one of the combined designs will be implemented in the field of VLSI systems to improve consumption power and sizing of integrated circuits. Increasing leakage power due to scaling down of device dimensions, supply and Leakage power dissipation is taken as the average of power dissipations obtained at all the possible input vectors of the CMOS circuit. The proposed techniques yield some advantageous features, which are presented as:

1) When logic 0 is applied at the input terminal of CMOS, the NMOS transistor will turn OFF and PMOS will turn ON. As a result, logic 1 will be available at the output node.

2) When logic 1 is applied at the input, NMOS turns ON and PMOS goes into the OFF state. Thus, there will be logic 0 at the output node. Power dissipation in CMOS transistors occurs mainly because of the device switching operations.

3) The dynamic and short-circuit power dissipation are jointly called switching power dissipation. Switching power dissipation arises due to the charging and discharging of output load capacitance during switching.

4) During charging and discharging operation, there is an inevitable energy loss of CV² for static CMOS circuits. During charging operation, the energy dissipation through the pull-up block from the power supply is equal to CV², of which half of the energy (0.5 CV²) is stored.

5) There are 4 possible combinations for a 2-input NAND; hence, the average of the four power dissipations gives the leakage power.

6) In the case of 4-input AOI, power dissipations corresponding to all the 16 combinations are averaged.

7) For a multiplexer, the average of 64 power dissipations is considered and for a full adder, the average of 8 power dissipations is considered to be the static power dissipated.

8) LECTOR uses two LCTs, which are self-controlled transistors.

9) LECTOR and LSSR present efficient reduction in leakage power like other leakage reduction techniques, such as sleepy stack, sleepy keeper, etc., along with the advantage of not affecting the dynamic power.

10) Since this technique does not require any additional control and monitoring circuitry and also in this technique, the exact logic state is in each case, the leakage power is measured by exciting both the circuits (Conventional and LECTOR) with the same set of input vectors.

11) Static or leakage power dissipation is leakage currents, reverse-biased currents and substrate injection currents, which flow through the transistors in their steady states.

12) This work presents a comparative analysis of CMOS Process Technology 180 nm to 32 nm and the simulation results of various circuits in CMOS Process Technology 180 nm to 32 nm shows a significant performance, overall concluding remark 32 nm yields high performance due to less power dissipation and lower propagation delay. Therefore, CMOS Process 32 nm Technology is highly suitable for high-speed and low-power VLSI applications with Lecter Technique.

Suggestions

1) Manuscript yields a new circuit technology and comparative study.

2) Simulation results show that the proposed approach improves leakage current characteristics and enhances battery life in various mobile computing, multimedia, wireless communication and low-power real applications.