Figure 1 illustrates a cross-sectional view of the investigated 5 nm FDSOI and PDSOI n-MSOFET. For both the FDSOI and PDSOI channel length was taken as identical, so that a fair comparison could be made. In Figure 1(a), Figure 1(b) the layout and placement of gate oxide, silicon layer, buried oxide, source and drain can be seen.

Figure 1. (a) 5 nm FDSOI Structure n-MOSFET (b) 5 nm PDSOI Structure n-MOSFET.

Major differences between the two devices occur in the silicon layer thickness (T_Si) and doping of the source, gate and drain regions. In FDSOI, an ultra-thin silicon layer was utilized to ensure better gate electrostatic control over the channel, which in turn helps to minimize leakage currents and Short-Channel Effects (SCEs) [18]. However, in PDSOI T_Si of significantly higher thickness was used as compared to FDSOI. Because it ensures that a floating body is created, which is the key characteristic of PDSOI, which supports higher drive current and dynamic threshold operation [19].

From Table 1, all the devices take advantage of ultra-thin gate oxide thickness (T_GOX). In case of base FDSOI the silicon layer thickness (T_Si) used was 1.5 nm which is approximately 1/4th of the channel length, in optimized variant it was slightly reduced to 1.3 nm in optimized FDSOI. For PDSOI the T_Si was 7.5 nm for base variant and 8 nm for optimized variant. The T_Si of PDSOI variants was estimated by utilizing the Depletion Region Width Equation. Source and Drain doping concentrations for all 4 devices were taken as identical so that a comparative study could be executed as closely as possible. However, channel doping was dissimilar between PDSOI and FDSOI. A higher doping level (1 × 10²⁰ cm⁻³) was utilized in PDSOI to assist partial depletion, suppress punch-through and leakage. In contrast, a light doping level (1 × 10¹⁰ cm⁻³) was used for FDSOI to ensure full depletion of the silicon film.

Table 1. Device specifications of base & optimized PDSOI and FDSOI.

Silvaco TCAD ATLAS environment was used for device simulations and modelling of the 5 nm PDSOI & FDSOI devices. To capture the complex behavior of these nanoscale devices, an extensive set of physical models was employed in the simulation environment. The Auger Recombination model (AUGER), Shockley-Read-Hall (SRH) were employed for carrier recombination and generation mechanisms. Auger Recombination model was also used to evaluate high current densities. Bandgap narrowing due to heavy doping in source & drain regions was simulated by including Bandgap Narrowing Model (BGN). The concentration-dependent carrier mobility phenomenon was modelled using the Concentration-Dependent Mobility Model (CONMOB). In addition, the degradation of mobility in the inversion layer was simulated using the Lombardi (CVT) model. In ultra-scaled devices effect of lateral electric field on mobility, velocity saturation becomes significant, Field-Dependent Mobility Model (FLDMOB) was utilized to predict this phenomenon in the 5 nm long, 8 nm and 1.3 nm thick silicon channels in PDSOI and FDSOI respectively. Finally, Selberherr’s impact ionization model (IMPACT SELB) was also utilized to account for short-channel effects which predict the breakdown characteristics of 5 nm devices. Different iterative numerical methods that are available in Silvaco TCAD were used to solve the devices in different biasing conditions. These arrays of models help to accurately capture the behavior of highly scaled SOI devices in this paper [20].

In this section, 4 parameters were varied on the base variant of 5 nm FDSOI n-type MOSFET to estimate an optimized variant. InFigure 2(a), T_Si varied from 1 nm to 3 nm, this showed that as the T_Si increases the corresponding curves shifts in the left. It means that as T_Si increases the threshold voltage (V_th) decreases, while the ON-current (I_ON) increases significantly. This happens because, with increasing T_Si the series resistance in the channel reduces whereas inversion charge density increases [21].

ForFigure 2(b), T_GOX varied from 0.1 nm to 1.7 nm. As T_GOX increases the corresponding I_ON decreases. Whereas the V_th slightly shifts toward the right which indicates that it increases but slightly. Thicker oxide decreases gate capacitance which results in weaker electric fields so less inversion charge that also means lower I_ON. Additionally, thicker T_GOX causes weaker gate control over the channel that means more voltage is required for inversion which increases the V_th [22]. InFigure 2(b), a crossover of the graphs can be seen around 0.8 V. This occurred due to combined effects of V_th shift, sub-threshold swing (SS) variation, and dissimilar inversion charge dynamics which make thicker oxide devices lag the thinner oxide devices. Because thinner oxide devices reach inversion saturation before thicker oxide devices in same gate voltage conditions comparatively. Figure 2(c) shows I-V characteristics in case of different source & drain doping. With increasing doping, the I_ON current increases. Because channel’s carrier conductivity increases with higher dopant [23]. FinallyFigure 2(d) shows variation of Work function from 4.6 eV to 5.5 eV. With increasing value of Work function V_th increases because the gate needs higher voltage to overcome the increased energy barrier for forming inversion layer. On the contrary, I_ON decreases with increasing Work function for less gate overdrive due to higher V_th.

This section varies the same parameters of the previous section on the base variant of 5 nm PDSOI n-type MOSFET to estimate an optimized variant. Figure 3(a) shows the effect of T_Si variation. Here, for T_Si above 7.5 nm the other 4 curves nearly overlap, this is because above a certain T_Si gate electric field is unable to influence the silicon body. That’s why for 9 nm, 10.5 nm, 12 nm, 13.5 nm the T_Si is overly thick to have any significant variation in drain current.

Figure 2. I_DS vs V_GS characteristics of 5 nm FDSOI (Base variant) for different parameter variations (a) Silicon thickness (b) Gate Oxide (c) Source & Drain doping (d) Work function.

InFigure 3(b) gate oxide thickness variation shows that for T_GOX = 0.1 nm where I_ON is higher than 5000 µA, which is nearly 2.3 times greater than FDSOI inFigure 2(b). This occurs due to the significant channel doping difference between the two types of devices as shown in Table 1. Other trends in the graph are likeFigure 2(b). Figure 3(c), Figure 3(d) vary source & drain doping, Work function. And the trends of the curves are similar to those inFigure 2(c), Figure 2(d).

Figure 3. I_DS vs V_GS characteristics of 5 nm PDSOI (Base variant) for different parameter variations (a) Silicon thickness (b) Gate Oxide (c) Source & Drain doping (d) Work function.

Figure 4 & Figure 5 focus on the comparison of I_DS/V_GS characteristics & SS of optimized variants of the devices. From Figure 4 and Table 2 in case of PDSOI variants, there was a 17.04% and 15.78% reduction in V_th and sub-threshold slope, respectively.

For FDSOI variants from Figure 5 and Table 2, there was a reduction of 6.6% and 11.04% reduction in V_th and SS respectively. Lower V_th facilitates lower power consumption and better performance. Comparison between investigated optimized variants of PDSOI and FDSOI shows that the PDSOI device had lower V_th and SS slope. This is because the changes in design parameters have greater influence on V_th and SS in PDSOI. Whereas in FDSOI it is more stable when changing the design criteria.

Figure 4. I_DS vs V_GS characteristics of 5 nm PDSOI (Optimized variant).

Figure 5. I_DS vs V_GS characteristics of 5 nm FDSOI (Optimized variant).

Leakage current for both PDSOI and FDSOI were lower than expected in spite of short channel effects. The I_DS was 1.049542 mA at 1.2 V for FDSOI (optimized) which is higher than the PDSOI (optimized), this results in higher Power Consumption, stronger drive strength & better signal integrity. In Figure 5 slope of the curve significantly decreases after 1 V compared to in the range of 0.6 V to 1 V. This FDSOI (optimized) with further increase in V_GS, the I_DS output curve tapers. But the PDSOI (optimized) the I_DS increases nearly in a proportional manner with increasing V_GS, demonstrating linear dependency in the strong inversion region. This difference arises due to partially-depleted and the fully-depleted SOI region.

Table 2 shows different performance parameters of base and optimized variants for both PDSOI and FDSOI. I_ON/I_OFF ratio for all variants is in the range of 10⁶ indicating highly efficient switching performance. This demonstrates excellent gate control and sub-threshold characteristics, which are crucial for high-performance devices.

Table 2. Performance parameters of base and optimized variants of PDSOI and FDSOI.

Figure 6 shows comparison of Electric Field profile for optimized PDSOI and FDSOI devices. For both cases there was sharp increase in magnitude of electric field near the source edge (0.005 µm) and a similar decrease near the drain edge (0.01 µm).

Figure 6. Electric field vs Channel Length profile of Optimized variants of PDSOI and FDSOI.

The PDSOI curve peaks at around 20 MV/cm and FDSOI around 7 MV/cm. Thicker silicon body of PDSOI lets larger lateral fields to develop enables boosting of ON-current drive. On the contrary, thin silicon body of FDSOI causes stronger gate coupling which limits field strength but improves electrostatic integrity. Spikes in the FDSOI curve are due to abrupt change in doping profiles of source-channel and channel-drain interface.

Figure 7 shows I_D vs V_D curves for increasing gate voltages (V_g) which is used to analyze Kink Effect in MOSFETs. The PDSOI MOSFET (optimized) inFigure 7(a) shows kink after V_D = 4.77 V whereas for FDSOI inFigure 7(b) no kink was seen for the range of applied voltages.

Figure 7. I-V curve for Drain Voltage of 7.2 V for optimized variant of (a) PDSOI (b) FDSOI.

InFigure 7(a), we can see kink appears in the PDSOI I_D-V_D graph, it is a direct manifestation of the floating-body effect. With increasing the drain voltage (V_D), high lateral electric field near the drain results in impact ionization for creating an electron-hole pair. As the electrons are attracted towards the drain, the created holes are pushed into the neutral floating body region [9][24]. The accumulation of these holes increases the potential level in the body, and thus reduces (V_th). This decrease in V_th facilitates the abrupt surge of the I_D, which results in a “kink” feature at about 4.77 V. But in FDSOI the fully-depleted thin body eliminates charge buildup that prevents any kink effect [25][26].

Various Gate Oxide materials were explored in search of better device characteristics as shown in Figure 8. Default material parameters of Silvaco TCAD (version 2016) were utilized for simulations of different gate oxide materials [20].While these parameters are widely used and provide reliable comparative insights, they may not fully capture process-dependent variations, interface trap densities, and material imperfections which may result in discrepancies with fabricated high-k/Si gate stacks. For PDSOI inFigure 8(a) there is much variation in V_th and I_DS but for FDSOI inFigure 8(b) the curves are much closer showing less variation. This is due to partial depletion effects and weaker electrostatic gate control in PDSOI and superior electrostatic gate control in FDSOI. Using high-k materials such as Ta₂O₅, HfO₂, ZrO₂ shows lower V_th and sub-threshold swing (SS) compared to other materials for PDSOI (from Table 3).

Figure 8. I_DS vs V_GS graph for different Gate Oxide materials of (a) optimized PDSOI (b) optimized FDSOI.

Table 3. Performance parameters of optimized PDSOI for various gate oxide materials.

In PDSOI V_th was 39.15%, 37.92% and 22.48% better for Ta₂O₅, HfO₂/ZrO₂ and Si₃N₄ respectively than SiO₂ (For optimized variant in Table 2 and Table 3). For FDSOI V_th was 0.826%, 0.937% and 2.496% better for Ta₂O₅, HfO₂/ZrO₂ and Si₃N₄ respectively than SiO₂ (For optimized variant in Table 2 and Table 4). FDSOI exhibits much better I_ON/I_OFF ratio compared to PDSOI (around 10⁹ and 10⁶ range in FDSOI and PDSOI respectively) for same set of gate oxide materials (from Table 3 and Table 4).

Table 4. Performance parameters of optimized FDSOI for various gate oxide materials.