The inverter is a power electronic device which converts DC power to AC power. Inverters are widely used in many types of applications, including renewable energies—especially photovoltaic (PV) and fuel cells [1] [2] —adjustable-speed drives [3] , uninterruptible power supplies (UPS) [4] , and more. The earliest inverter topology invention is a two-level inverter [5] [6] ; since the output voltage is not close to a sinusoidal wave shape, this topology is only suitable for application in industrial applications and power systems which require low power quality. This topology has evolved to a multilevel inverter topology, due to its bad performance when operating in high power and medium-/high-voltage applications at high switching frequency. The idea of the “multilevel inverter” was introduced in 1975, beginning with the three-level inverter [7] [8] .

Multilevel inverters have attracted the interest of researchers and academia, given that they are crucial in high-power and high-voltage applications as a result of their ability to deliver higher output voltage quality compared to traditional two-level inverter topologies. Multilevel inverters are reported to produce superior output voltage quality, as the generated output voltage takes a staircase form which closely approximates a sinusoidal waveform shape with an increasing number of levels [7] - [16] . The smoothness of the output voltage waveform can be enhanced by increasing the number of levels in the multilevel inverter, which consequently reduces the total harmonic distortion (THD) in the output waveform.

Many types of multilevel inverter topologies have been introduced [9] [10] , with the three primary topologies being diode-clamped or neutral point clamped, flying capacitor, and cascaded H-bridge. Recently, attention has been directed to minimising the number of components in multilevel inverters to reduce voltage stress, lower harmonic distortion, lower switching frequency and switching losses, and improve efficiency in both single-source and multiple-source configurations, as described in [10] . However, as the number of output voltage levels increases, a greater number of switches, DC sources, gate driver circuits, heat sinks, and protective components are required; this leads to higher costs and greater control system complexity.

Researchers have introduced numerous forms of modulation approaches for multilevel inverters. These modulation techniques are classified into two categories: low switching frequency modulation techniques and high switching frequency modulation techniques. Examples of low switching frequency modulation techniques include selective harmonic elimination (SHE) [11] , nearest vector control (NVC), and nearest level control (NLC) [12] , whereas high switching frequency modulation techniques include multireference or multicarrier pulse-width modulation (PWM) [13] - [15] and space vector modulation (SVM) [16] . Hybrid modulation refers to the integration of the two types of modulation techniques.

Field programmable gate arrays (FPGAs) have been widely implemented in power electronics systems due to their flexibility, high processing speed, and capability to execute complex control algorithms in real time [17] - [25] . Although FPGA-based controllers have been extensively applied in various power electronics systems—such as DC-DC converters [18] [19] , inverters [20] - [23] , rectifiers [24] , and cycloconverters [25] —limited research focuses on closed-loop single-phase transistor-clamped H-bridge (TCHB) multilevel inverter systems using FPGA. Existing studies primarily address conventional multilevel inverter topologies or emphasise simulation-based analysis, with minimal hardware validation for TCHB configurations with FPGA integration specifically. This gap highlights the need for experimental performance evaluation of single-phase TCHB multilevel inverters controlled by FPGA, to enhance their applicability in real-world power conversion systems.

While FPGAs have been widely used in other power electronic applications, their role in this work extends to real-time implementation of a discrete proportional-integral (PI) controller, enabling fast dynamic response, precise switching control, and reduced harmonic distortion. Therefore, the novelty of this work lies in the integration of FPGA-based closed-loop control for the single-phase five-level TCHB inverter topology. To the best of our knowledge, this is the first reported study that experimentally validates a closed-loop TCHB multilevel inverter using FPGA, addressing a gap in prior research that has largely been limited to simulation or conventional inverter topologies.

In this context, the TCHB multilevel inverter emerges as a more effective alternative to conventional multilevel topologies. The diode-clamped inverter requires a large number of clamping diodes, leading to higher switching losses and increased design complexity. The flying capacitor topology demands numerous capacitors, which not only raises system cost but also introduces reliability concerns. Similarly, the cascaded H-bridge inverter depends on multiple isolated DC sources, limiting its suitability for compact applications. In contrast, the TCHB multilevel inverter achieves the same level output with fewer switches and DC power supplies, thereby simplifying the hardware design while maintaining efficient and reliable performance.

This paper presents the detailed design of a multicarrier sinusoidal pulse-width modulation (SPWM) technique in order to produce five distinct voltage levels in the TCHB multilevel inverter. The closed-loop system of the TCHB multilevel inverter is first modelled and simulated in MATLAB/Simulink; this is followed by the development and testing of a hardware prototype controlled using FPGA. The performance of the TCHB multilevel inverter, obtained from both the simulation and the experimental implementation, is then evaluated and compared with that of a conventional H-bridge inverter.

Figure 1 illustrates the five-level TCHB inverter configuration, which comprises a conventional H-bridge inverter with an auxiliary switch and four diodes functioning as bidirectional switches connected to the centre of the DC capacitors. With appropriate switching management, the auxiliary switch will be capable of generating half the level of the DC supply voltage, or ±1/2 V_dc.

The multicarrier SPWM technique used here compares the sinusoidal reference waveform with the triangular waveform of the carrier signals to generate the PWM switching signals. Two triangular carrier signals and one reference sinusoidal signal are used for multicarrier SPWM signal generation for the five-level TCHB inverter, as illustrated in Figure 2(a) . The reference sinusoidal signal has a frequency of 50 Hz. The negative waveform of the reference sinusoidal signal is lifted using the modulus block in MATLAB/Simulink, as illustrated in Figure 2(b) . In a comparison of the reference sinusoidal signal with the upper and lower sides of the triangular carrier signals, the PWM switching signals are generated through the application of combinational logics.

The amplitude modulation ratio M_a of the proposed five-level TCHB inverter can be expressed as:

$M_a=\frac{A_M}{2A_C}$ (1)

where A_M is the reference signal’s peak value, while A_C is the peak-to-peak value of the carrier signals used. The behaviour of the evaluated five-level TCHB inverter is obtained when the modulation index is more than 0.5 but less than or equal to 1 (0.5 < M_a ≤ 1). If the modulation index is equal to or less than 0.5 (0.5 ≤ M_a), the behaviour of the proposed inverter mimics that of a three-level inverter; this was due to only the lower carrier wave being compared with the reference signal, and thus the output voltage produced is only half the DC bus voltage. When the amplitude of the reference signal exceeds the amplitude of the upper carrier wave and the modulation index is greater than 1 (M_a > 1), over-modulation occurs.

1: ON; 0: OFF.

Table 1 shows the output levels of TCHB inverter based on the operational condition of the switches, which were either 1 (on) or 0 (off). This topology can generate five different levels of output voltage waveforms: +V_dc, +V_dc/2, 0, −V_dc/2, and −V_dc. Only two switches are operated at one time. Through the combinations of the on and off states of the switches (S₁ - S₅) depicted in Table 1 , the inverter output voltage v_inv can be expressed as:

$v_{inv}=V_{dc}\left(S_4-S_2\right)\left\{\frac{1}{2}{S}_5+\left|S_1-S_2\right|\cdot \left|S_3-S_4\right|\right\}$ (2)

The proposed five-level TCHB inverter is a buck converter whose average output voltage v_o is characteristically always lower than the input DC voltage V_dc. Equation (3) gives the peak value of the proposed inverter’s output voltage:

$v_o=M_a{V}_{dc}$ (3)

The FPGA used for hardware development is the Altera DE2 Board. The advantages of DE2 FPGA include affordability, many flexible onboard features, freedom in designing both hardware and CAD tools, and the ability to implement a wide range of digital circuit designs. A Cyclone II 2C35 FPGA device is included together with the aid of various hardware resources and components incorporated on-board, including 33,216 logic elements (LE), 483,840 RAM bits, 35 embedded multipliers, and 475 user I/O pins.

The main goal of the control strategy for the proposed TCHB multilevel inverter is the production of sinusoidal output voltage with low harmonic distortion under proper control techniques. A proportional–integral (PI) control algorithm is implemented as the feedback controller for the proposed inverter. A basic closed-loop feedback system with a PI controller for the inverter may include a sensor, an analog-to-digital converter (ADC), and a digital PWM as shown in Figure 3 . The PI controller feeds on the error between the reference voltage and the measured output voltage. If y(t) is the measured variable and r(t) is the reference variable, the error e(t) is:

$e\left(t\right)=r\left(t\right)-y\left(t\right)$ (4)

In continuous time, the input e(t) and the output u(t) of the PI algorithm relate as follows:

$u\left(t\right)=K_{p}e\left(t\right)+K_i{\displaystyle \underset{0}{\overset{t}{\int }}e\left(t\right)\text{d}\tau }$ (5)

where K_p and K_i are the proportional gain and the integral gain, respectively.

The PI control algorithm is designed in a discrete form to enable implementation on FPGA. By applying the Tustin approximation, the integral term is discretized, and the discrete PI controller can be expressed as:

$U\left(z\right)-U\left(z\right)z^{-1}=K_{1}E\left(z\right)+K_{2}E\left(z\right)z^{-1}$ (6)

where $K_1=\left(K_p+\frac{K_i{T}_s}{2}\right)$ and $K_2=\left(\frac{K_i{T}_s}{2}-K_p\right)$

The desired output response is achieved by tuning the K_p and K_i gains of the PI controller. After the tuning process is done, with K_p = 10, K_i = 1 using T_s = 1 μs sampling time, the discrete PI controller is implemented as:

$u\left(n\right)=u\left(n-1\right)+10.0000005e\left(n\right)-9.9999995e\left(n-1\right)$ (7)

To ensure stable operation, the PI controller must be protected against integral windup which is undesired condition by preventing the integral value from exceeding the required limit.

An appropriate ADC must be chosen to convert the analogue voltage signal into digital, as there is no integrated ADC on the DE2 FPGA board, and the selected ADC chip should be inexpensive. The feedback signal from the inverter or the measured voltage is sensed by a voltage sensor (LV25-P) and then fed at an 8-kHz sampling rate to an ADC0808 (8-bit). The measured (digital) voltage is then compared with the sinusoidal lookup table (LUT) (the sine-wave reference), with the resultant signal subsequently fed to the digital PI controller. The implementation of digital PI controller using FPGA is illustrated in Figure 4 .

To prevent a short circuit across the input voltage source, the dead-time t_dead is included in the gating signals of the switches. (Dead-time is usually called delay time or blanking time.) For practicality, these signals are given to the gate driver circuit to trigger the switching devices (insulated gate bipolar transistors, or IGBTs). The magnitude of t_dead is set to 1 µs and applied between the PWM signals.

The FPGA-based PWM generator is designed using Verilog HDL and through schematic design entries. The design, synthesis, and simulation are conducted on Quartus Prime software. Five PWM output signals with dead-time are assigned and sent to the gate drive circuit to trigger the proposed inverter circuit. In addition, the Quartus Prime software includes a tool for the designer to view the designed circuit in schematic diagram through register transfer level (RTL) Viewer; the RTL graphics are presented for the design of the PWM generator with a PI control algorithm—shown in Figure 5(a) —and the PWM logic module—illustrated in Figure 5(b) .

This paper presents the design and implementation of a single-phase five-level TCHB inverter using FPGA. This topology uses a multicarrier PWM technique consisting of two carrier signals and one reference signal to generate the PWM switching signal. The simulation results show that the THD decreases when the number of inverter levels increase; thus, the proposed five-level inverter is better than two-level and three-level inverters. By integrating a suitable filter, operating at an appropriate switching frequency, and applying an effective control strategy, the adopted inverter produces sinusoidal output voltage and current. Additionally, using only an inductive low-pass filter, the overall THD for both load voltage and load current waveforms remains below 3% for modulation indices in the range of 0.5 < M_a ≤ 1. When the amplitude modulation ratio is set to be less than or equal to 0.5, the proposed inverter will act like a three-level inverter.

The authors thank Universiti Teknikal Malaysia Melaka for supporting this work.