The literature investigation shows, that surface and interface in CdTe photovoltaic devices play an important role in the determining of the solar cell efficiency. The morphological characteristics of the CdS thin film were investigated by AFM and SEM. It has been revealed that the morphology of CdS films has a considerable impact on their overall properties. This was especially noted in the devices, wherein the surface roughness and grain boundaries affected the recombination in the films. The 3D AFM image topography was used to investigate CdS topography on different substrates. In Figure 2, 3D AFM images of CdS on glass, on CdTe thin film, on CdTe/CdO interface and CdO on CdS thin film are presented.

The surface of all samples reveals a distinct distribution of grains with a uniform granular topography. The surfaces consist of hundreds nano-sized grains when CdS deposited on CdTe and CdTe/CdO, and the root mean square roughness (S_q)

of the deposited CdS thin films was 284 nm and 222.4 nm, respectively, which indicates the formation of smooth and well-connected grains on the film (Table 1). When CdS is deposited on glass and CdO on CdS, the values of S_q are 31.1 nm and 29.3 nm, respectively. A low influence on S_q was found for CdS and CdO samples in comparison with CdS deposited on CdTe and CdTe/CdO surfaces. The same situation is observed and for the average surface roughness (S_a). For all films, skewness (S_sk) shows negative values that specify more valleys than peaks, and the surface is more planer. We point out that, when CdS is deposited on glass and CdO on CdS, the films surfaces are more homogenous and flatter. This can be explained by an antireflection effect of the CdO layer. As the refractive index of CdO is about 2.5, of CdS is 2.4 and of CdTe about 3.0, there is better matching of the refractive index at the air/CdS/ CdO/CdTe interfaces (S_q = 29.3 nm) compared to the air/CdS/CdTe interface (S_q = 284.0 nm). Moreover, after CdO nanolayer deposition, additional interference fringes in the CdO appears in the CdTe absorption (300 - 1200 nm) region due to the flat CdO on CdS interfaces, which can impact the light intensity in the bulk of the absorber. Moreover, method for interfacial defect passivation could change the interface morphology and modify recombination rate, one would expect higher recombination for a rough interface (S_q = 284.0 nm) rather than a smooth interface (S_q = 29.3 nm).

We conclude that the surface morphology of the films is influenced by both, the nature of the substrate and CdO on CdS provoked a decreasing of the surface roughness.

The literature analysis suggests that an intrinsic interlayer formed at the interface suppress the surface recombination [29] . Figure 3 displays a plain view SEM image showing the morphology of CdO on CdS surface (a) and a cross-section of a CdS/CdO/CdTe heterostructure (b). After the deposition of CdO thin film of about 8 - 11 nm on the CdS, the surface became more homogeneous. The deposited CdO layer encloses the surface of the CdS layer, smoothers the surface relief and helps block impurities diffusion from CdS in the CdTe layer. The SEM cross-section image of CdS/CdO/CdTe heterostructure (Figure 3(b)) shows the big grains for CdTe that not densely packed.

Also, voids and a non-uniformity of the CdS and CdTe films thickness at the

The root means square roughness—S_q, The average surface roughness—S_a, Skewness—S_sk, Bearing Mean diameter—D.

interface are observed. The cross-section inset confirms the non-uniform accumulation of CdO at the interface of CdS/CdTe. The presence of the void’s at CdS internal surface (Figure 3(b)) indicates that the CdO penetrate within the voids and reduce the imperfections on its surface. The evolutions of the elemental distribution across the depth of CdS/CdTe and CdS/CdO/CdTe devices are shown in Figure 4.

The EDX elemental distribution profiles of both CdTe devices show the Cd-L, Te-L, S-K lines. The EDX signals of Cd (Lα1) and S (Kα1) at 3.1 eV and 2.3 eV were observed. In addition, CdS/CdO/CdTe devices show O-K line (yellow) at 0.5 eV. The results of EDX line scans of cross-section of the CdS/CdO/CdTe device show non-uniform distribution of Cd-L (blue) and Te-L (green) lines in the elemental profile compared to CdS/CdTe heterostructure, where distinct regions can be seen. The image of CdS/CdO/CdTe device reveals complex interfacial chemistry, with a bilayer in place of the CdS. CdO film on the CdS layer suppresses the S interdiffusion from CdS into CdTe film and prevents the formation of solid solution with a lower bandgap that results in poor quantum efficiency.

The J-V characteristics for the best SnO₂/CdS/CdTe and SnO₂/CdS/CdO/CdTe devices under 100 mW∙cm⁻² illuminations, 300 K are shown in Figure 5(a).

The photovoltaic parameters, the fill factor (FF), short circuit current density (J_sc), open circuit voltage (V_oc) and the efficiency of the conversion (η), estimated from these dependencies are presented in Table 2. Comparison of the photovoltaic parameters of solar cells based on CdTe revealed that solar cells with i-layer are the best. To further show the utility of i-CdO approach on short circuit current density, FF and open circuit voltage, a number of nine CdS/CdTe structures with different thicknesses of CdO insulating layer were compared. According to

Figure 5(b), for a thicker i-layer than 11 nm, J_sc decreases because degrades the drift electric field for carrier transport.

Through the theoretical analysis it is shown that the insertion of a thin insulating layer between the two semiconductors of an n⁺-p structure improves the efficiency in the same way as for a metal-insulator semiconductor (MIS) solar cell, if the discontinuity in the conduction bands constitutes a barrier for excited electrons. In our devices, the CdO interfacial layer with thickness greater than 11 nm modifies the morphology and composition of CdS and either plays no role or is disadvantageous.

For the open circuit voltage (Figure 6(a)), a sharp increase is observed at 5 - 11 nm thicknesses of the CdO layer and at thickness greater than 11 nm, it remains constant at 0.79 V. From these dependencies, for p-i-n heterojunction devices it follows that the optimal thickness of i-CdO is between 8 nm and 11 nm. It can be assumed that when CdO is too thin, it acts as a tunneling layer for the current, while when it is thicker, it acts as a blocking layer. So, sputtered i-CdO nanolayer as an interface engineering approach led to an enhancement of both J_sc and V_oc by 5% and 25%, respectively. The series (R_s) and shunt (R_sh) resistances in this paper were calculated from the line slope of the J-V curves at the open-circuit voltage and short-circuit current points, respectively. The values of the R_s for both CdS/CdTe and CdS/CdO/CdTe devices are equally with 8.8 × 10² Ω∙cm² and 1.1 × 10² Ω∙cm², respectively, while the shunt resistances reached the values of 0.54 × 10³ Ω∙cm² and 0.5 × 10³ Ω∙cm². The R_s value for CdS/CdO/CdTe device was decreased. The R_sh value for both devices has about the same value and smaller than of the series resistance because of the non-idealities, mainly impurities near the p-n heterojunction, which cause partial shorting of the heterojunction.

Low shunt resistance causes power losses in the photovoltaic devices by providing an alternate current path for the light-generated current. Such a diversion reduces the amount of current flowing through the photovoltaic device junction and reduces the voltage. The low values of shunt resistance usually result from manufacturing defects.

Analysis of the dark current-voltage characteristics (Figure 6(b)) show that the introduction of i-CdO nanolayer between the CdS and CdTe layers leads to a shift in the I-V curves but not of the changing of the current transport mechanism. The built-in voltage increases from 0.51 V to 0.65 V but the reverse saturation

current decreases from 7.5 × 10⁻¹⁰ A to 1.5 × 10⁻¹⁰ A. The increase in the built-in voltage of the devices with i-CdO nanolayer is due to the change of the work function of the n-doped electron transport layer. Finally, we can conclude that the same model current mechanism can be applied for both CdS/CdTe and CdS/CdO/CdTe heterojunctions solar cells as the diode quality factor is n = 1.9 and n = 1.8, respectively. The decrease of n by 0.1 for CdS/CdO/CdTe solar cell is indication of the enhancement of open circuit voltage and current density values, with 0.11 V and 1.9 mA/cm², respectively. It is therefore suggested that the recombination mechanism of CdS/CdTe photovoltaic cells is primarily SRH mechanism, achieved by deep trap states in space charge region of CdTe. The energy level can provide both electrons and holes. When n varies from 1 to 2, defects play the role of deep trap level. When the change of n is getting closer to 1, the recombination mechanism begins to fall in inter-band recombination, mostly in the neutral region. Surface recombination will make the change of n value more than 2. The recombination at grain boundaries should also be considered, causing the loss of carrier collection and reducing the voltage value. At the CdS/CdTe interface, there is a 9.7% lattice mismatch between the cubic CdS and the cubic CdTe. Such a high lattice mismatch causes considerable defects at the CdS/CdTe interface. Therefore, both devices exhibit SRH recombination as the dominant current transfer mechanism across the interface because the large conduction (ΔE_C = (0.23 … 0.3) eV and valence (ΔE_C = (0.67 and 0.74) eV bands offsets block thermal currents [30] . ΔE_C is a vital factor affecting carrier transport and recombination.

To identify the nature of traps from J-V-T measurements, we briefly present analysis of the dark J-V-T characteristics. Figure 7(a), Figure 7(b) presents the Arrhenius plots of the saturation current density (J_s) of both devices, measured in the temperature range of 173 K - 331 K. The temperature dependencies revealed in Figure 7(a), Figure 7(b) by the slopes of Arrhenius plots provide useful insight into the presence of two defect levels for CdS/CdTe and one defect

level for CdS/CdO/CdTe devices. By analysis of J_s evolution with reciprocal temperature, we distinguish regions where J_s changes were fitted by linear function. In both CdS/CdTe and CdS/CdO/CdTe devices, in the lower temperature region of J_s, the defect level with activation energies of 0.24 eV and 0.25 eV was revealed, while in the higher J_s temperature region of CdS/CdTe, device a defect level with activation energies of 0.45 eV is depicted.

The saturation current density reveals that their changes with temperature in CdS/CdTe device follow the rule of recombination as a dominant carrier transport mechanism, via the defect levels located at 0.45 eV and 0.24 eV above the valence band edge of CdTe, while in the CdS/CdO/CdTe device only via the defect level located at 0.25 eV. Therefore, to gain better understanding into the carrier density and deep defects in the CdTe absorber, as well as, the effect of possible defects at the heterojunction interface for the devices with and without CdO interface nanolayer, CV and TAS measurements were conducted. The CV and TAS results were compared only for the reference CdTe/CdS device (i.e., without CdO interface layer) and for the best cell, employing an 8 - 11 nm thick CdO interface nanolayer.

There are three main interfaces for CdTe thin-film photovoltaic devices: TCO/CdS interface, CdS/CdTe interface, and CdTe/Ni interface. As the main p-n junction of CdTe thin-film photovoltaic devices, the CdS/CdTe interface depletion region is the key in photoelectric conversion of CdTe thin film photovoltaics, and is the core of the entire device. To understand the J_sc and V_oc CdS/CdTe photovoltaic devices improvements by engineering of very thin insulating CdO wide-bandgap semiconducting material presented in previous paragraph, J-V-T and C-V measurements at different temperatures has been applied to both CdS/CdTe and CdS/CdO/CdTe devices. Also, admittance measurements C-ω-T give information on the widths of the space charge region of the device and on the contribution of trap levels to the capacitance of the device. High-frequency and low-temperature value of capacitance provide the total width of the depletion region, while the low frequency—the depletion width diminished by the response of traps, which are fast enough to respond to the AC signal of the admittance meter [26] . From bulk capacitance we extract the depletion layer width and the apparent free carrier density according to the equations: [30]

w = ε A C , (1)

N ( W ) = − 2 q ε A 3 [ d ( 1 / C 2 ) d V ] − 1 (2)

where ε = ε_o∙ε_r, ε_r is the dielectric constant of CdTe, ε_o is the permittivity of free space, q is the electron charge, W is width of the depletion region, A is the area of the device. We assume a one-sided device, in which the dominant capacitance response originates from the edge of the depletion region in the more intrinsic layer, and assumes that the temperature is high enough that the carriers can be rapidly transported into and away from the edge of the depletion region at the applied AC frequency. The application of DC bias (V) changes the value of the depletion width in CdS/CdO/CdTe device because at the interface appear a material with the relative permittivity ε different from of CdS and with a higher N_CV density concentration. Figure 8(b) shows 1/C² = f(V) for the CdS/CdO/CdTe structures at 100 kHz and 1 MHz frequencies. Evidently, from this figure, the (C²-V) relation is generally nonlinear. However, each curve can be fitted approximately with a broken line consisting of one linear region. The slopes of the straight lines increase with frequency. The interception of the lower voltage straight lines with the voltage axis results in different values for the built-in voltage. As the N_CV density concentration is not constant throughout the depletion layer, the different values for the built-in voltage were obtained. The results from the experimental measurements listed in Table 3 show that at 0.1 MHz frequency the main charge carriers transport processes take place in the depletion region of (5.2 - 5.3) μm width for CdTe/CdS thin film devices. The CdO nanolayer passivates the shallow defects resulting in a higher N_CV density concentration at both low and higher frequencies and the carriers transport processes take

place in the narrower depletion region of 4.7 μm width. If the depletion region width, at 1 MH_Z frequency, for one of the CdTe/CdS thin film device slightly increases but for another decrease, then for the device with i-CdO nanolayer for both lower and higher frequencies, the depletion region width decreases. A more interesting feature is with built-in voltages at 1 MHz, for both types of devices, the V_bi values are increased. An increase of about 0.5 V was observed in the case of the device with i-CdO nanolayer. It is well known that in a semiconductor, V_bi equals the potential difference across the depletion region in thermal equilibrium. In thermal equilibrium, no external voltage is applied to the device. Moreover, the Fermi energy is constant throughout the heterostructure and the built-in voltage equals the difference between the Fermi energies, respectively in the buffer and the absorber, divided by the elementary charge. Figure 8(a) presents the defect profiles that show the typical U-shaped form commonly reported in literature [31] [32] , with a minimum at a profiling distance of 2.0 - 5.5 µm. Both profiles exhibit a significant increase in the defect profile toward the junction and toward the bulk of the sample. Trying to understand differences between the low frequency and high frequency profiles, it can be seen that the curves have an almost identical shape, but seem to be shifted by a distance.

An apparent depth dependence of the resulting doping concentration is often attributed to charge contributions of deep trap levels because their charge state depends on the band bending. The minimum N_CV densities concentration is in the range of ~9 × 10¹³ cm⁻³ to ~1 × 10¹⁴ cm⁻³ and increases toward negative bias voltages, that is, toward higher apparent depth within the CdTe. The N_CV densities were determined from the bottom of the U-shaped curve at zero bias. For the CdS/CdO/CdTe devices there is an observable increase in the N_CV density profile inside the device and a decrease of a value of the width in comparison with non-engineering of the interface devices. Also, when the depletion region enters the front and the back-contact regions, the N_CV concentration there rapidly rises. Another observation is a difference between the built-in voltages (V_bi). From one side, this suggests that performance degradation of CdS/CdTe without not-engineering interface can arise from lower N_CV density due to CdCl₂ treatment.

According to the previous investigation [33] , CdCl₂ activation treatment is responsible for the formation of a V_Cd shallow acceptor complex, which leads to an increase in the doping densities in CdTe devices.

However, the excess of Cl can lead to the formation of self-compensating Cl_Te donors [34] [35] . This effect could explain the decrease in the N_CV density concentration which can be directly translated into the V_OC decreases, as presented previously. Through the deposition of i-CdO nanolayer when the device is reverse biased the majority charge carriers are stopped to push away from the junction and less ions are left at the junction. This beneficial situation reduced the available V_Cd (shallow acceptor centers) and the doping density of the CdS increases, which lead to an increase in V_OC. Since C-V technique gives information about the kinetics of carrier transport, then with AS, the characteristics of the majority carrier trapping defects can be determined for solar cell materials and devices. If deeper carrier traps are present, the band bending in the SCR causes the Fermi level E_F to cross the trap level E_t at some distance from the interface, at the crossing point x_t shown in Figure 9.

An applied small AC voltage with the frequency f = ω/2π causes the electric charge accumulated by traps to oscillate in the vicinity of crossing point x_t. In the case of low frequency, the trap related capacitance is C_t = C_lf, where C_lf is the low frequency capacitance, while at high frequency measurements give the junction capacitance, i.e. depletion area capacitance C_d = C_hf, where C_hf is the high frequency capacitance. Accordingly, in the case of a single majority carrier trap level, the total junction capacitance can be described by the equation:

C d + C l f − C d 1 + ω 2 τ 2 (3)

where τ is the characteristic trapping time that depends of the trap density N_t [36] . Figure 10 presents the C-f-T curves measured in the temperature range from 50 K to 320 K. The values of the capacitances for the device without i-CdO nanolayer are slightly smaller and temperature dependent in comparison with of the device with nanolayer at the interface.

The inflection frequency ω_o can be obtained from the analysis of the first derivative of the capacitance, dC/dω, which demonstrates a maximum at the frequency ω_o. A small AC oscillating voltage with the frequency 0.2 MHz causes the electric charge accumulated by traps to oscillate in the vicinity of this crossing point. The trapped electric charge follows the applied voltage oscillations and contributes to the total capacitance only if their frequency does not exceed the trap characteristic frequency ω_o. In the case of a small trap concentration N_τ, the characteristic frequency ω_o for the charging and discharging of defect levels is ω_o = 1/τ [37] . The temperature dependence of the inflection frequency ω_o is determined by the following equation [37] :

ω o ( T ) = 2 e t ( T ) = 2 N C , V v t h σ n , p exp ( − E A k T ) = 2 ξ 0 T 2 exp ( − E A k T ) (4)

where e_t is the emission rate, N_C,V is the effective density of states in the conduction and valence band, ν_th is the thermal velocity of the minority carriers at the interface, σ_n,p is the capture cross-section for electrons and holes, E_A = E_t – E is the activation energy of the defect level E_t with respect to the band edge E, k is the Boltzmann constant, and ξ₀ covers all the temperature independent parameters [38] . The activation energy of a defect level E_A was obtained from the temperature frequency dependence of the capacitance spectra i.e., from the Arrhenius plot of the quantity ln(ω_o/T²) versus 10³/T. From the Arrhenius plot of the ln(ω_o/T²) versus 10³/T presented in Figure 11 were estimated the activation energy of the defect levels. According to the TAS theory [38] , the majority carrier to the frequency of the AC signal is limited by the modified dielectric relaxation frequency (ω_o = W/d∙ε_r∙ρ), where ρ and ε_r are the material resistivity and relative permittivity, respectively, W is the depletion width, and d is the absorber thickness. For ω < ω_o, the CdTe in the quasineutral region behaves as a conductor with a bulk conductance, while for ω > ω_o, it behaves like a capacitor with a bulk capacitance. The extracted activation energies for CdS/CdTe are 0.43 eV and 0.20 eV.

Also, using admittance spectroscopy technique, authors of [39] [40] [41] [42] found a thermal ionization energy of 0.23(3) eV in CdTe attributed to the V_Cd defects, which is in good agreement with first principles investigations. In CdTe, Cd vacancies act as acceptors with two ionization energy levels, the first ionization state V C d ( 0 / − 1 ) and the second ionization state V C d ( − 1 / − 2 ) have been reported [43] [44] . The activation energy of 0.20 eV defect level could be located above the valence band maximum for both heterojunction devices. According to the theory, wide-band gap semiconductors show self-compensation, that is the spontaneous formation of acceptor-type intrinsic defects to compensate or passivate donor-type.

The CdCl₂ activation step is standard and vital process in fabricating high

efficiency PV devices. From a theoretical point of view, chlorine is predicted to promote further p-type doping of CdTe via a shallow donor Cl_Te defect with an ionization energy below the conduction band.

So, defect energies extracted from the admittance spectroscopy for CdS/CdTe devices (0.43 eV and 0.20 eV), CdS/CdO/CdTe (0.22 eV) and J-V-T (0.45 eV and 0.24 eV), (0.25 eV) measurements, respectively are in good agreement. The experimentally measured activation energies values from plot of capacitance transients and J-V-T techniques are in good agreement and therefore, we assume that the activation energy of 0.43 eV occurs due to the formation of cadmium vacancies V_Cd and acceptor complexes V_Cd – Cl, which continuously shift Fermi level towards valence band and decrease resistivity. Several publications [45] [46] [47] have been reported a deep trap in the range 0.43 - 0.54 eV above the valence band maximum [48] [49] [50] [51] . These experimental values are in good agreement with our value highlighted by TAS measurements in CdS/CdTe device without interface engineering and belonging to the complex (Cl_Te – V_Cd)⁻¹ that consists of a C l T e + 1 impurity and a V C d − 2 defect that are below to acceptor (Cl_Te – V_Cd)⁻¹ complex (AX-center).

Taking into account the activation energy values of 0.43 eV and 0.20 eV presented in Figure 11 and assuming the energy diagram of CdTe for the CdS/CdTe device presented in Figure 12, the energetic position of these two defects 0.43 eV (AX-center) and 0.22 eV (acceptor-like defect) are situated in the space charge region. The analysis of the current-voltage characteristics in the higher and lower temperature regions of CdS/CdTe device indicates the presence of the traps with activation energy of 0.45 eV and 0.24 eV, respectively and is assigned to the recombination process as a dominant current flow mechanism. For the device with CdO insulating layer at the interface, the only a trap with activation energy of 0.25 eV was revealed. The identified traps act as a recombination centers for electrons. The TAS investigation revealed the same deep levels in CdS/ CdTe and CdS/CdO/CdTe photovoltaic devices, among which the most dominant

was a trap with an activation energy of 0.20 eV and 0.22 eV. This defect has about the same value as energy states determined by J-V-T analysis. Based on the literature review and TAS system database, we assigned it to the formation of cadmium vacancies V_Cd. This obviously confirms that V_Cd defects act as a recombination center and, therefore, have a significant impact on the current flow mechanism in the low temperature region.

The engineering of interface of the CdS/CdTe heterostructure with CdO thicknesses about 8 - 11 nm “kills” the deep (Cl_Te – V_Cd)⁻¹ AX-center and improve both J_sc and V_oc parameters, but keeps the defect with the activation energy values of 0.20 eV and 0.22 eV in both CdS/CdTe and CdS/CdO/CdTe devices.

In summary, we can assume that the concentration of free charge carriers is determined by the vacancies of cadmium V_Cd defects with activation energies of 0.20 eV (CdS/CdTe) and 0.22 eV (CdS/CdO/CdTe) devices that agree well with values of the publications [51] [52] [53] . The typical dopant concentrations are ~10¹⁴ to 10¹⁵ cm⁻³ for polycrystalline CdTe which is limited by the number of V_Cd present in CdTe [54] . The CdS/CdTe interface is one of the critical device regions in CdTe photovoltaic devices and its properties are not clearly understood at this time, and influence on device stability still unknown.