The double gate structure as shown in Figure 1 consists of two gate electrodes: front gate and back gate controlling a conducting channel in between.

DG-MOSFETs can easily be scaled down beyond 50 nm technology node due to better immunity to short channel effects. This is because of the enhanced gate to channel coupling capacitance provided by the two gates on either side of the channel. The DG-MOS architectures can be designed with low doped channels which give better carrier mobility and hence, better switching time. The leakage power dissipation caused by off-state currents are minimized in DG-MOSFETs as compared to bulk MOSFETs. The DG-MOSFETs have better current driving

capability and hence they can be used at much lower threshold and input voltages and consequently power consumption is reduced in DG-MOSFETs. Since no part of the channel is too far away from the two gates, channel current is better controlled by the gate electrodes that gives ideal sub-threshold slope required for sub- threshold region based circuit design [6] [7] [8].

In order to minimize the drastic increase of short channel effects in highly scaled DG-MOSFETs, very thin oxides and highly doped channels are required which results in very high electric field at the interface. This high electric field leads to the formation of potential well sufficiently steep for inducing quantization of carrier energy levels. The charge carriers then follow the physics of tightly confined particles and they require quantum mechanical treatment. In DG-MOSFETs, carriers are confined due to two main phenomenon: first one is the confinement caused by very high electric field at the interface when oxide thickness is very less (t_ox < 3 nm) (known as electric field induced quantum confinement and second one is due to the confinement caused by ultra-thin Si film thickness (t_si < 10 nm) (known as t_si induced structural quantum confinement). The effect of these confinements on the device characteristics such as threshold voltage and drain current are quite important. For DG-MOSFETs with Si-film thickness less than 10nm, quantum effects must be incorporated in the analysis and modeling of such device architectures [9] [10] [11].

The device structure is designed as per the ITRS guidelines and simulated using Silvaco ATLAS Deckbuild editor. Bohm Quantum Potential (BQP) model has been used for incorporating quantum effects; incomplete ionization has been activated in order to account for impurity freeze-out at low temperature. Mobility degradation due to surface roughness scattering and acoustic phonon scattering and concentration dependent mobility is taken care by Lombardi CVT Mobility Model. Shockley-Read-Hall (SRH) model has been used to take recombination effects into account. The impact ionization of carrier under high lateral electric field along with Fermi carrier statistics has also been activated in simulation. The Constant Current Method (CCM) has been used for the threshold voltage extraction

and calculation of DIBL [12] [13] [14]. V_t is extracted from transfer characteristics by measuring the gate voltage at drain current value I D = W L * 10 − 7 A , where W is channel width and L is channel length. The W L ratio used in the work is 50 [15] [16]. The device parameters selected for simulation are as per the guidelines of International technology roadmap for semiconductors [17] (see Table 1).

Figure 2 represents threshold voltage (V_t) and leakage current (I_off) variation as a function of channel length for different values of operating temperature (T_op). It is evident from the figure that the threshold voltage decreases and leakage current increases with increase in operating temperature at a fixed channel length.

The threshold voltage (V_t) dependence on temperature is modeled as [18] :

∂ V t ∂ T = φ m s ∂ T + 2 ∂ φ f ∂ T + γ 2 φ f 2 + ∂ φ f ∂ T (1)

where φ m s is metal-substrate contact potential, T is operating temperature, φ f is substrate Fermi potential, γ is body effect coefficient.

As the temperature increases, the first and third term in the equation decreases and second term increases resulting in a net decrease in threshold voltage.

As the threshold voltage decreases with increase in temperature, the leakage current (I_off) increases as per the following equation [19] :

I o f f = I o e V G S − V t n V T [ 1 − e − V D S V T ] (2)

where I o = W μ o C o x V T 2 e 1.8 L and thermal voltage V T = K T q C_ox is gate oxide capacitance, μ_o is the carrier mobility and n is the subthreshold swing coefficient.

In Figure 3, variation of I_on current and transconductance with channel length for different values of operating temperature is plotted. It can be observed that both the quantities decrease with increasing temperature at a fixed channel length. This is because I_on is proportional to μ(T) and (V_GS-V_t(T))² term and g_m is proportional to μ(T) and (V_GS-V_t(T)) term. As the temperature increases, (V_GS-V_t(T)) term increases because threshold voltage (V_t(T)) decreases as discussed earlier and μ(T) term decreases due to phonon scattering at higher temperature (T > 300 K). The decrease in mobility dominates the term (V_GS-V_t(T)) which causes I_on current and transconductance to decrease at higher temperature [20].

Figure 4 shows the variation of subthreshold slope (SS) and I_on-I_off ratio with channel length for different values of operating temperature. It is clear from the plot that the subthreshold slope and I_on-I_off ratio degrades with increasing temperature at a fixed channel length. This may be due to the fact that as the temperature increases, I_on current decreases due to mobility reduction caused by phonon scattering and I_off current increases because of increase in junction leakage current which approximately doubles for every 10˚C rise in temperature.

Figure 5 shows the variation of DIBL with channel length for different values of operating temperature. DIBL increases with increasing temperature at a fixed channel length. This is due to the fact that the threshold voltage degrades when temperature increases.

From Figure 6, the threshold voltage can be found decreasing with increasing channel doping concentration due to the degradation in mobility caused by surface roughness scattering and acoustic phonon scattering. Since, threshold voltage increases with increasing channel doping concentration, the leakage current must reduce according to Equation (2) [21].

In Figure 7, it is observed that I_on current and transconductance decreases with increasing channel doping concentration. This is because of mobility degradation due to columbic scattering and increase in threshold voltage due to increase in Fermi potential of the bulk at high channel doping concentration [22].

Figure 8 represents the variation of I_on-I_off ratio and subthreshold slope (SS) as a function of channel length for different values of channel doping concentration. It is observed that I_on-I_off ratio and SS improves at higher channel doping concentration as leakage current (I_off) is reduced to a great extent [23] [24].

Figure 9 shows that variation of DIBL with channel length for different values of channel doping concentration. It is found that DIBL is lower for higher channel doping concentration at a fixed channel length due to threshold voltage degradation at high doping concentration.

In Figure 10, the variation of threshold voltage (V_t) and leakage current (I_off) at different channel length for different values of oxide thickness is plotted. It is clear from the plot that the threshold voltage increases with decreasing oxide thickness for a fixed channel length. This can be attributed to quantum mechanical effects due to which peak of the inversion layer is found at a finite distance, d_m away from the interface resulting in increased effective oxide thickness [25]. The effective increase in oxide thickness is given by Equation (3):

Δ T O X , Q M = ε O X ε S i d m (3)

Also, due to splitting of allowable energy levels into discrete sub-bands with energy levels above that of the classical conduction band edge, energy band gap increases which results in increased effective Fermi potential. This leads to increase in surface potential and thus in increased value for threshold voltage.

From Figure 11, the leakage current can be observed increasing with increase in oxide thickness as the threshold voltage decreases with increased oxide thickness.

Figure 11 shows the variation of I_on and transconductance with channel length for different values of oxide thickness. It is evident from the plot that both the quantities decrease with increase in oxide thickness at a fixed channel length. This is because of reduced gate to channel coupling capacitance with increase in oxide thickness.

Figure 12 represents the variation of I_on-I_off ratio and SS with channel length for different values of oxide thickness. As I_on current decreases and I_off current increases with increase in oxide thickness, I_on-I_off ratio and SS degrades with increase in oxide thickness.

Figure 13 shows the variation of DIBL with channel length for different values of oxide thickness. It is observed that device with thicker oxide suffers more from DIBL effects. This is due to reduced gate to channel coupling which allows drain to control the channel charges.

Figure 14 represents the variation of threshold voltage and leakage current with channel length for different Si film thickness values. It is observed from the figure that with decreasing Si film thickness at a fixed channel length, threshold voltage increases. This is because of the fact that the energy quantization increases in channel region with decreasing Si film thickness, t_si.

The leakage current is observed to increase with increase in Si film thickness at a given channel length due to reduced gate to channel coupling capacitance at higher values of Si film thickness.

Figure 15 shows the variation of I_on current and transconductance with channel length for different values of Si film thickness. I_on current decreases with decrease in Si film thickness due to increase in energy quantization in channel region

that leads to enhanced threshold voltage values. The transconductance value is found to decrease with increase in Si film thickness due to reduced gate to chan- nel coupling.

In Figure 16, variation of SS and I_on-I_off ratio with channel length for different Si film thickness values is shown. The I_on-I_off ratio is found to decrease with increasing Si film thickness. This is because both I_on and I_off current increase with increasing Si film thickness but increase in I_off is more as compared to I_on. Therefore, the ratio I_on-I_off decreases with increase in Si film thickness. The SS is observed to improve with decreasing Si film thickness as I_on-I_off ratio is enhanced when Si film thickness is reduced.

Figure 17 shows the variation of DIBL as function of channel length for different values of Si film thickness. It can be observed that the DIBL effect is negligible for longer channel length devices. The DIBL effects are more prominent

in devices with thicker channel. This is due to weak gate to channel coupling which allow drain to enhance the control over channel charges.