Multimedia systems play an essential part in our daily lives and have drastically improved the quality of life over time. Adders are the fundamental data path blocks in media signal processors present in electronic devices such as cellphones, radios, televisions, and computers. These devices require low-area, low-power reconfigurable adders to process real-time greedy computation algorithms such as discrete cosine transform [1] [2] [3], inverse discrete cosine transform, fast Fourier transform, etc. Configuring an architecture on-the-go such as dynamic configuration, allows a system to be dynamically modified during its normal operation without the need for resetting the remaining circuitry or removing any reconfigurable blocks for programming. The reconfiguration also optimizes the necessary component count and power consumption, making it suitable for data path components in media signal processing, networking, and cryptography [4] - [18].

Several reconfigurable adder architectures have been proposed for MSP applications. A reconfigurable adder uses an 8-bit carry generation block as the basic unit and a prefix-based controlled carry grouping logic to reduce power consumption [9]. A reconfigurable carry-skip adder for minimal energy and high-speed performance was proposed in [11]. A reconfigurable SQRT-CSLA with a modified ripple carry adder for high speed is proposed in [12]. A hybrid reconfigurable adder architecture combined with variants like RCA, CLA, CSLA for reduced power and area is proposed in [13]. A reconfigurable adder targeted for Binary/BCD addition for high-speed performance was proposed in [19].

In media signal processing, the data path switching, such as in adders and multipliers, can substantially consume switching power. We aim to configure the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. This paper focuses on a novel 64-bit reconfigurable adder architecture for MSP applications with reduced area and power consumption. Moreover, the reconfiguration of the proposed design is more dynamic than the existing design [11] and requires less area and power.

The proposed 64-bit dynamic reconfigurable adder includes the second stage of partition to increase the reconfigurability. This dynamic configuration is a unique feature that has not been explored in previous designs [9] [11] [12] [13] [19]. Multimedia Signal Processors perform millions of complex computations within seconds; therefore, they require a high-speed, low-power data-path to store and compute the signals that arrive at it. The high switching activity in the data-path components contributes to higher power consumption, which has been minimized in the proposed adder by using a new reconfiguration scheme. It gives more flexibility and control over the choice of partition, which minimizes data path hardware usage by turning off the unused components and routing the signals efficiently, leading to lower power consumption.

Section 2 describes the logic behind the 64-bit CSMT reconfigurable adder and then the 64-bit dynamic CSMT reconfigurable adder.

The Carry Select Modified Tree adder is a multiplexer-based design with low latency and low energy consumption [20] [21]. The proposed 64-bit dynamic reconfigurable adder adopts the CSMT based adder to build the basic reconfigurable block. Figure 3(a) shows a bit slice of the multiplexer-based adder that is designed using the CSMT principle proposed in [21]. Consider a simple addition function, say

Y = A + B

where Y = Y_w−1….Y₀, A = A_w−1….A₀ and B = B_w−1….B₀ represents W-bit binary numbers. A multiplexer-based design is implemented by defining a new recoding where,

A i r = A i ⋅ B i

_{B i r = A i + B i}

This creates a don’t care condition, thereby reducing the complexity of the circuit. The equations for sum and carry can be expressed as,

S i + 1 = C i ( B i r + A i r ) + C i ( A i r + B i r )

C i + 1 = C i ⋅ B i r + C i ⋅ A i

Figure 7 shows how the adder is configured to perform two 32-bit additions using the CSMT based 64-bit MSP adder. The highlighted green boxes indicate each of the individual 32-bit adders. The control signals P0 and P1 are set to 0 and 1 respectively to perform the 32-bit additions concerning the partition commands provided in Table 1. The control signals P0 and P1 activate the 8-bit block (highlighted in black) to be partitioned as (2-b, 6-b) sub-blocks and ensures that no carry bit is propagated among these sub-blocks. The drawback of this adder is that it can have only a single configuration model at a given time.

A second stage configuration is introduced in the proposed 64-bit dynamically reconfigurable adder to solve this problem. Figure 8 shows the proposed CSMT based dynamically reconfigurable adder that has additional configuration options. Let us take the two 32-bit addition case. As a supplement to the first stage 32-bit partition, the second stage control signals Si1, Si2, Si3/Si4 allow the user to configure additional partitions to the adder if needed. Among the two 32-bit adders, either of the adders can be further partitioned to perform two 16-bit or four 8-bit additions.

In Figure 8, we take the LSB 32-bit adder for partitioning. The MSB still performs the original 32-bit addition. The green highlighted sections indicate the first stage 32-bit adders obtained by setting P0 = 0 and P1 = 1, therefore splitting the 8-bit block (highlighted in black) into (2-b, 6-b) sub-blocks. The red

arrows indicate the active data path signals, and the grey arrows indicate the inactive data path signals. The second stage of partition is activated when the first stage of configuration is either 32-bit or 16-bit.

In Figure 8 the XOR output is 1 for the 32-bit configuration (P0 = 0, P1 = 1). The second stage control signal Si1 is set to 0, Si2 is set to 0, and Si3 is set to 1, according to Table 3. The enable signal En = 1. The corresponding partition selection is then sent to P2, either selecting the LSB or the MSB based on the Si2 value. For an example of two 16-bit adder configurations, the 6-bit block (highlighted in black) is split as (3-b, 3-b) sub-blocks and no carry propagation occurs among the sub-blocks. The 16-bit blocks are highlighted in pink within the 32-bit green block.

The dynamically reconfigurable adder has two advantages:

1) Internal partitions can be run-time configured without having to replace the adder blocks.

2) The MSP adder's power consumption is significantly reduced since the MSP adder computes only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. The performance evaluation of the CSMT based 64-bit MSP adder, the CSMT based dynamically reconfigurable 64-bit MSP adder and the 64-bit MSP adder [11] in terms of area, power and delay are explained in the next section.

Table 4 shows the area, power, and delay comparison for the three designs. They are 1) the 64-bit MSP adder [11], 2) the proposed CSMT based 64-bit MSP adder, and 3) the proposed dynamically reconfigurable CSMT based 64-bit MSP adder. All three designs were implemented, verified, synthesized, and optimized in CMOS 180 nm technology.

In comparison with the 64-bit MSP adder [11]:

1) the proposed CSMT based 64-bit MSP adder has a 23% reduction in area and a 53.1% reduction in power, and

2) the proposed dynamically configurable CSMT based 64-bit MSP adder has a 15.7% reduction in area and a 59.2% reduction in power.

When compared with the proposed CSMT based 64-bit MSP adder, the dynamically configurable CSMT based 64-bit MSP adder has a 13% reduction in power. The area is increased by 9.4% because of the second stage of partition

that configures the MSP computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used.

It is nearly impossible to achieve a design that takes up less area, consumes less power, and runs at high speed simultaneously since there is always a trade-off. This paper has presented a low-area, low-power CSMT based 64-bit MSP adder, which can be run-time reconfigured to perform either eight 8-bits, four 16-bits, two 32-bits, or one 64-bit addition based on the partition command. This circuit is further optimized in power by adding a second stage of partition to make the design more dynamically reconfigurable. It gives the user flexibility and control over the choice of partitioning for media signal processing. The proposed CSMT based 64-bit MSP adder achieves a 23% reduction in area, 53% reduction in power with a slight 4% increase in delay than the 64-bit MSP adder. Next, the proposed dynamically configurable CSMT based 64-bit MSP adder consumes less power by 59.2% and 13% compared to the 64-bit MSP adder and the proposed CSMT based 64-bit MSP adder, respectively. The proposed dynamically configurable CSMT based 64-bit MSP adder requires less area by 15.7% than the 64-bit MSP adder. All three designs have close critical path delays; however, the low-area and low-power feature of the proposed dynamically configurable CSMT based 64-bit MSP adder makes it practical for media signal processing applications.

The authors declare no conflicts of interest regarding the publication of this paper.

Allwin, P.S. and Chen, C.-I.H. (2021) A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder. Journal of Computer and Communications, 9, 54-69. https://doi.org/10.4236/jcc.2021.93004