TITLE:
Logical Function Decomposition Method for Synthesis of Digital Logical System Implemented with Programmable Logic Devices (PLD)
AUTHORS:
Mihai Grigore Timis, Alexandru Valachi, Alexandru Barleanu, Andrei Stan
KEYWORDS:
Combinational Circuits; Static Hazard; Logic Design; Boolean Functions; Logical Decompositions
JOURNAL NAME:
Circuits and Systems,
Vol.4 No.7,
November
8,
2013
ABSTRACT: The paper consists in the use of some logical functions
decomposition algorithms with application in the implementation of classical
circuits like SSI, MSI and PLD. The decomposition methods use the Boolean
matrix calculation. It is calculated the implementation costs emphasizing the
most economical solutions. One
important aspect of serial decomposition is the task of selecting “best candidate” variables for the G
function. Decomposition is essentially a process of substituting two or more input variables
with a lesser number of new variables. This substitutes results in the
reduction of the number of rows in the truth table. Hence, we look for
variables which are most likely to reduce the number of rows in the truth table as a result of
decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input
variables. The only available parameter to evaluate its activity is the number
of “l”s or “O”s that it has in the
truth table. If the variable has only “1” s or “0” s, it is the “best candidate” for decomposition, as it is practically
redundant.