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M. Mansour and N. Shanbhag, “A 640-mb/s 2048-bit Programmable Ldpc Decoder Chip,” Solid-State Circuits, IEEE Journal of, Vol. 41, 2006, pp. 684-698. doi:10.1109/JSSC.2005.864133

has been cited by the following article:

• TITLE: Quasi-cyclic Random Projection Code and Hardware Implementation

  AUTHORS: Saifeng Shi, Min Wang, Xinlu Lu, Jun Wu

  KEYWORDS: Quasi-cyclic; Mapping Matrix; Random Projection Code; Hardware Implementation

  JOURNAL NAME: Communications and Network, Vol.5 No.3C, November 7, 2013

  ABSTRACT: Random Projection Code (RPC) is a mechanism that combines channel coding and modulation together and realizes rate adaptation in the receiving end. Random projection code’s mapping matrix has significant influences on decoding performance as well as hardware implementation complexity. To reduce hardware implementation complexity, we design a quasi-cyclic mapping matrix for RPC codes. Compared with other construction approaches, our design gets rid of data filter component, thus reducing chip area 7284.95 um2, and power consumption 331.46 uW in 0.13 um fabrication. Our simulation results show that our method does not cause any performance loss and even gets 0.2 dB to 0.5 dB gain at BER 10-4.