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P. Nuzzo, P. Van Der Plas, G. De Bernardinis, R. Van Der Perre, L. Gyselinckx and B. Terreni, “A 10.6Mw/ 0.8Pj Power-Scalable 1Gs/S 4B Adc in 0.18/Spl Mu/M Cmos with 5.8Ghz Erbw,” The 43rd ACM/IEEE of the Design Automation Conference, San Francisco, 2006, pp. 873-878.

has been cited by the following article:

• TITLE: Design and Implementation of Double Base Integer Encoder of Term Metrical to Direct Binary

  AUTHORS: Takialddin A. Al Smadi

  KEYWORDS: ADC; CMOS VLSI; High Speed Data Converters; Code

  JOURNAL NAME: Journal of Signal and Information Processing, Vol.4 No.4, November 1, 2013

  ABSTRACT: The digital processing signal is one of the subdivisions of the analog digital converter interface; data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of low power operation power with 70 mVt 1.8 V A/D converter from the power dissipated during operation in the 5 GHz range. Average offset is used to minimize the effect of the bias of a comparator. This paper contains the 8-bit encoder of the metrical term code to direct binary code decreasing power consumption, which is shown by results and comparison with other designs using computer simulation. The results of the flash ADC time-interleaved are a more significant improvement in terms of power and areas than those previously reported.