Article citationsMore>>

Y. Wu, Z. Y. Wen, and Z. P. Jiang, “Low voltage separation model and discussion for electrophoresis chip,” Opto-Electronic Engineering, Vol. 29, pp. 27-33, 2002.

has been cited by the following article:

• TITLE: Fabrication of Si-PDMS Low Voltage Capillary Electrophoresis Chip

  AUTHORS: Wenwen GU, Zhiyu WEN, Zhongquan WEN, Yi XU, Fengfei LIANG, Xiaoguo HU

  KEYWORDS: Low Voltage, Arrayed-Electrode, Si-PDMS, CE Chip

  JOURNAL NAME: Engineering, Vol.1 No.2, August 24, 2009

  ABSTRACT: This paper discusses the fabrication of Si-PDMS low voltage capillary electrophoresis chip (CE chip). Arrayed-electrode which is used to apply low separation voltage is fabricated along the sidewalls of the separation channel on the silicon based bottom part. Isolation trenches, which are placed surrounding the arrayed-electrode, insure the insulation between the arrayed-electrode, as well as arrayed-electrode and liquid in the micro channel. Polydimethylsilicone (PDMS) is used as the cover. PDMS and silicon based bottom part are reversible sealed to attain Si-PDMS low voltage CE chip. Experiments have been done to obtain optimum electrophoresis separation condition: separation voltage is 45V, switch time is 2s and the Phe and Lys electrophoresis separation is successful.