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R. Holsmark, S. Kumar, M. Palesi and A. Mejia, “HiRA: A Methodology for Deadlock Free Routing in Hierarchi cal Networks on Chip,” Proceedings of 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Die go, 10-13 May 2009, pp. 2-11.

has been cited by the following article:

• TITLE: Cluster Based Hierarchical Routing Algorithm for Network on Chip

  AUTHORS: U. Saravanakumar, R. Rangarajan, R. Haripriya, R. Nithya, K. Rajasekar

  KEYWORDS: System on Chip; Network on Chip; Deterministic and Adaptive Routing Algorithms; Mesh; Torus

  JOURNAL NAME: Circuits and Systems, Vol.4 No.5, August 30, 2013

  ABSTRACT: This paper presents a new logical mechanism called as Cluster Based Hierarchical Routing (CBHR) to improve the efficiency of NoC. This algorithm comprises the following steps: 1) the network is segmented logically into clusters with same size or different sizes; 2) algorithms are assigned for internal and global routing; 3) routers working functions are modified logically to support local and global communication. The experiments have conducted for CBHR algorithm for two dimensional mesh and torus architectures. The performance of this mechanism is analyzed and compared with other deterministic and adaptive routing algorithms in terms of energy, throughput with different packet injection ratios.