TITLE:
Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study
AUTHORS:
Mona M. Fouad, Hassanein H. Amer, Ahmed H. Madian, Mohamed B. Abdelhalim
KEYWORDS:
Current Mode Logic (CML); CMOS; Testing; Stuck-At Faults
JOURNAL NAME:
Circuits and Systems,
Vol.4 No.4,
August
12,
2013
ABSTRACT: This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.