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M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono and H. Yamada, “A GHz MOS Adaptive Pipeline Technique Using MOS Current-Mode Logic,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 6, 1996, pp. 784-791. doi:10.1109/4.509864

has been cited by the following article:

• TITLE: Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

  AUTHORS: Mona M. Fouad, Hassanein H. Amer, Ahmed H. Madian, Mohamed B. Abdelhalim

  KEYWORDS: Current Mode Logic (CML); CMOS; Testing; Stuck-At Faults

  JOURNAL NAME: Circuits and Systems, Vol.4 No.4, August 12, 2013

  ABSTRACT: This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.