TITLE:
Study on Test Compaction in High-Level Automatic Test Pattern Generation (ATPG) Platform
AUTHORS:
Ayub Chin Abdullah, Chia Yee Ooi
KEYWORDS:
Automatic Test Pattern Generation (ATPG); Constraint Logic Programming (CLP); Verilator; Circuit-Under-Test (CUT); Test Compaction
JOURNAL NAME:
Circuits and Systems,
Vol.4 No.4,
August
6,
2013
ABSTRACT: Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.