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J. C. Osborne, “Stability analysis of an nth power digital phase-locked loop-part I: First-order DPLL,” IEEE Transaction Communications, Vol. 28, pp. 1343-1354, August 1980.

has been cited by the following article:

• TITLE: TDTL Based Frequency Synthesizers with Auto Sensing Technique

  AUTHORS: Mahmoud AL-QUTAYRI, Saleh AL-ARAJI, Abdulrahman AL-HUMAIDAN

  KEYWORDS: Time-Delay Tanlock Loop, Frequency Synthesizer, Phase Lock Loop, Indirect Synthesis

  JOURNAL NAME: International Journal of Communications, Network and System Sciences, Vol.2 No.5, August 21, 2009

  ABSTRACT: This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.