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Y. B. Choi and X. Yuan, “A 3.5-mW 2.45-GHz Frequency Synthesizer in 0.18 μm CMOS,” IEEE International Symposium on Radio-Frequency Integration Technology, 9 January-11 December 2009, pp. 187-190.

has been cited by the following article:

• TITLE: A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

  AUTHORS: Fatemeh Talebi, Hassan Ghafoorifard, Samad Sheikhaei, Sajjad Shieh Ali Saleh

  KEYWORDS: ZigBee; Frequency Synthesizer; Phased Locked Loop; Injection Locking Technique

  JOURNAL NAME: Circuits and Systems, Vol.4 No.3, July 1, 2013

  ABSTRACT: A low power low phase noise frequency synthesizer with subharmonic injection locking is proposed for ZigBee applications. The PLL is based on a ring VCO to decrease area and production cost. In order to improve phase noise performance, a high frequency injection signal of which frequency varies with channel number is used. The circuit is designed in TSMC 0.18 μm CMOS technology and simulated in ADS (Advanced Design System). The phase noise at 3.5 and 10 MHz offsets is -116 and -118 dBc/Hz, respectively, and total circuit consumes 2.2 mA current.