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C. S. Ding, C. Y. Tsui and M. Pedram, “Gate-Level Power Estimation Using Tagged Probabilistic Simulation,” IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, 1998, pp. 1099-1107. doi:10.1109/43.736184

has been cited by the following article:

• TITLE: Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

  AUTHORS: Omnia S. Ahmed, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, Hassanein H. Amer, Ahmed H. Madian

  KEYWORDS: Dynamic Power Estimation; Logic Pictures; CMOS Digital Logic Circuits; Toggle Rate; Unit-Delay Model

  JOURNAL NAME: Circuits and Systems, Vol.4 No.3, June 27, 2013

  ABSTRACT: In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.