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V. G. Oklobdzija, D. Villeger and S. S. Liu, “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach,” IEEE Transactions on Computers, Vol. 45, No. 3, 1996, pp. 294-306. doi:10.1109/12.485568

has been cited by the following article:

• TITLE: High Speed Digital Oscillator Implementations Based on Advanced Arithmetic and Architecture Techniques

  AUTHORS: Ali Shatnawi, Mufleh Shatnawi

  KEYWORDS: Digital Oscillator; Single-Output Digital Oscillator; Multiple-Output Digital Oscillator; Advanced Arithmetic Techniques; Hardware Implementation

  JOURNAL NAME: Circuits and Systems, Vol.4 No.3, June 26, 2013

  ABSTRACT: The advances of digital arithmetic techniques permit computer designers to implement high speed application specific chips. The currently produced digital circuits have demonstrated high performance in terms of several criteria, such as, high clock rate, short input/output delay, small silicon area, and low power dissipation. In this paper, we implement several sinusoidal generation methods to optimize their performance and output using advanced digital arithmetic techniques. In this paper, the implementations of advanced digital oscillator structures with and without pipelining are proposed. The synthesis results of the implementation with pipelining have proven that it is superior to other sinusoidal generation methods in terms of the maximum frequency and signal resolution. Hence, this method is used in the design of the proposed digital oscillator chip.