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H. Sasaki, M. Ono, T. Ohguro, S. Nakamura, M. Satio and Iwai, “1.5 nm Direct-Tuneling Gate Oxide Si MOS FETs,” IEEE Transactions on Electron Devices, Vol. 43, No. 8, 1996, pp. 1233-1242.

has been cited by the following article:

• TITLE: A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits

  AUTHORS: Tarun Kumar Gupta, Kavita Khare

  KEYWORDS: Footerless Domino Logic; Subthreshold Leakage; Gate Oxide Tunneling; Leakage Current

  JOURNAL NAME: Circuits and Systems, Vol.4 No.2, April 18, 2013

  ABSTRACT: A new circuit technique for 65 nm technology is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type leakage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 10.9% to 44.76% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 25℃ and 110℃ temperatures the maximum leakage power saving of 98.9% is achieved when compared to standard footerless domino logic circuits.