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J. Cong, G. Han and Z. Zhang, “Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 9, 2006, pp. 986-997.

has been cited by the following article:

• TITLE: A Reconfigurable Network-on-Chip Datapath for Application Specific Computing

  AUTHORS: Joshua Weber, Erdal Oruklu

  KEYWORDS: Reconfigurable Computing; Network-on-Chip; Network Simulators; Polymorphic Computing

  JOURNAL NAME: Circuits and Systems, Vol.4 No.2, April 17, 2013

  ABSTRACT: This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.