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H. Vahedi, S. Gregori and R. Muresan, “On-Chip Power Efficient Current Flattening Circuit,” Journal of Circuits, Systems, and Computers, Vol. 18, No. 3, 2009, pp. 565-579. doi:10.1142/S0218126609005332

has been cited by the following article:

• TITLE: Design of Secure Microsystems Using Current-to-Data Dependency Analysis

  AUTHORS: Haleh Vahedi, Radu Muresan, Stefano Gregori

  KEYWORDS: Secure Microsystems; Differential Power Analysis Attack; Countermeasure; Current Flattening Circuit

  JOURNAL NAME: Circuits and Systems, Vol.4 No.2, April 17, 2013

  ABSTRACT: This paper presents a method for designing a class of countermeasures for DPA attacks based on attenuation of current variations. In this class of countermeasures, designers aim at decreasing the dynamic current variations to reduce the information that can be extracted from the current consumption of secure microsystems. The proposed method is based on a novel formula that calculates the number of current traces required for a successful DPA attack using the characteristics of the microsystem current signal and the external noise of the measurement setup. The different stages of the proposed method are illustrated through designing an example current flattening circuit. Meanwhile validity and applicability of the proposed formula is verified by comparing theoretical results with those obtained experimentally for the example circuit. The proposed formula not only estimates the required level of attenuation for a target level of robustness defined by design requirements, it also predicts the effectiveness of a countermeasure using simulation results therefore dramatically reducing the time to design of secure microsystems.