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S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar and V. De, “Ultra-Low Voltage Circuits and Processor in 180 nm to 90 nm Technologies with a Swapped-Body Biasing Technique,” IEEE International Digest of Technical Papers. Solid-State Circuits Conference, Vol. 1, 2004, pp. 156-157.

has been cited by the following article:

• TITLE: A 0.4 V Bulk-Driven Amplifier for Low-Power Data Converter Applications

  AUTHORS: R. Rezaei, A. Ahmadpour, M. N. Moghaddasi

  KEYWORDS: Pseudo Operational Transconductance Amplifier (P-OTA); Bulk-Input; Ultra Low-Voltage (ULV); Sample and Hold (S/H) Circuit

  JOURNAL NAME: Circuits and Systems, Vol.4 No.1, January 29, 2013

  ABSTRACT: This paper presents the design of an ultra low-voltage (ULV) pseudo operational transconductance amplifier (P-OTA) that is able to operate with a single supply voltage as low as 0.4 V. The proposed circuit is based on the bulk-driven technique and use of cross-coupled self-cascode pairs that boosts the differential DC gain. The stability condition of this structure for the DC gain is considered by definition of two coefficients to cancel out a controllable percentage of the denominator. This expression for stability condition yield optimized value for the DC gain. Also, as the principle of operation of the proposed technique relies on matching conditions, Monte Carlo analyzes are considered to study of the behavior of the proposed circuit against mismatches. The designed P-OTA have a DC gain of 64 dB, 212 KHz unity gain bandwidth, 57phase margin that is loaded by 10 pF differential capacitive loads, while consume only 16 μW. Eventually, from the proposed P-OTA, a low-power Sample and Hold (S/H) circuit with sampling frequency of 10 KS/s has been designed and simulated. The correct functionality for this configuration is verified from –30℃ to 70℃. The simulated data presented is obtained using the HSPICE Environment and is valid for the 90 nm triple-well CMOS process.