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G. Manganaro, S. UngKwak, S. H. Cho and A. Pulincherry, “A Behavioral Modelling Approach to the Design a Low Jitter Clock Source,” IEEE Transactions on Circuit and Systems II, Vol. 50, No. 11, 2003, pp. 804-814.

has been cited by the following article:

• TITLE: A Novel Time Domain Noise Model for Voltage Controlled Oscillators

  AUTHORS: Li Ke, Peter Wilson, Reuben Wilcock

  KEYWORDS: Voltage Controlled Oscillators; Noise Model; Simulation

  JOURNAL NAME: Circuits and Systems, Vol.4 No.1, January 29, 2013

  ABSTRACT: This paper describes a novel time domain noise model for voltage controlled oscillators that accurately and efficiently predicts both tuning behavior and phase noise performance. The proposed method is based on device level flicker and thermal noise models that have been developed in Simulink and although the case study is a multiple feedback four delay cell architecture it could easily be extended to any similar topology. The strength of the approach is verified through comparison with post layout simulation results from a commercial simulator and measured results from a 120 nm fabricated prototype chip. Furthermore, the effect of control voltage flicker noise on oscillator output phase noise is also investigated as an example application of the model. Transient simulation based noise analysis has the strong advantage that noise performance of higher level systems such as phase locked loops can be easily determined over a realistic acquisition and locking process yielding more accurate and reliable results.