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A. Tajalli, E. Vittoz, Y. Leblebici and E. J. Brauer, “Ultra Low Power Sub-Threshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept,” Proceedings of the European Solid-State Circuit Conference, Munich, September 2007, pp. 281-284.

has been cited by the following article:

• TITLE: Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

  AUTHORS: Sanjeev Rai, Ram Awadh Mishra, Sudarshan Tiwari

  KEYWORDS: CMOS Integrated Circuits; CMOS Logic Circuit; Dynamic Threshold MOS (DTMOS); Power-Delay Product; Source-Coupled Logic (SCL); Sub-Threshold CMOS; Sub-Threshold SCL; Ultra-Low-Power Circuits; Weak Inversion LP-LV(Low Power-Low Voltage)

  JOURNAL NAME: Circuits and Systems, Vol.4 No.1, January 25, 2013

  ABSTRACT: This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.