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S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee and A. M. Ionescu, “Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design,” IEEE Transactions on Electron Devices, Vol. 51, No. 11, 2004, pp. 1772-1782. Hdoi:10.1109/TED.2004.837369

has been cited by the following article:

• TITLE: New Model for Drain and Gate Current of Single-Electron Transistor at High Temperature

  AUTHORS: Amine Touati, Samir Chatbouri, Nabil Sghaier, Adel Kalboussi

  KEYWORDS: Single-Electron Transistor (SET); Master Equation; Orthodox Theory; Tunnel Current; Thermionic Current; SIMON

  JOURNAL NAME: World Journal of Nano Science and Engineering, Vol.2 No.4, December 11, 2012

  ABSTRACT: We propose a novel analytical model to describe the drain-source current as well as gate-source of single-electron transistors (SETs) at high temperature. Our model consists on summing the tunnel current and thermionic contribution. This model will be compared with another model.