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M. Dehan, J.-P. Raskin, I. Huynen and D. VanhoenackerJanvier, “An Improved Multiline Analysis for Monolithic Inductors,” IEEE Transactions on Solid-State Circuits, Vol. 37, No. 1, 2002, pp. 77-80.

has been cited by the following article:

• TITLE: On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

  AUTHORS: El-Sayed A. M. Hasaneen, Nagwa Okely

  KEYWORDS: Low Noise Amplifier; On-Chip Inductor; Noise Figure; Cascade Amplifier; Scattering Matrix

  JOURNAL NAME: Circuits and Systems, Vol.3 No.4, October 30, 2012

  ABSTRACT: This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.