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P. Servati, D. Striakhilev and A. Nathan, “Above-Threshold Parameter Extraction and Modeling for Amorphous Silicon Thin-Film Transistors,” IEEE Transactions on Electron Devices, Vol. 50, No. 11, 2003, pp. 2227-2235. doi:10.1109/TED.2003.818156

has been cited by the following article:

• TITLE: Influence of Extended Bias Stress on the Electrical Parameters of Mixed Oxide Thin Film Transistors

  AUTHORS: Winnie P. Mathews, Rajitha N. P. Vemuri, Terry L. Alford

  KEYWORDS: Electrical Stress; a-IGZO; Thin Film Transistors; Degradation; Threshold Voltage; Drain to Source Resistance; Power Factor; Equivalent Circuit

  JOURNAL NAME: Circuits and Systems, Vol.3 No.4, October 30, 2012

  ABSTRACT: This paper investigates the variation of electrical characteristic of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) under gate bias stress. The devices are subjected to positive and negative gate bias stress for prolonged time periods. The effect of bias stress time and polarity on the transistor current equation is investigated and the underlying effects responsible for these variations are determined. Negative gate stress produces a positive shift in the threshold voltage. This can be noted as a variation from prior studies. Due to variation of power factor (n) from two, the integral method is implemented to extract threshold voltage (vt) and power factor (n). Effective, mobility (ueff), drain to source resistance (RDS) and constant k' is also extracted from the device characteristics. The unstressed value of n is deter-mined to be 2.5. The power factor increases with gate bias stress time. The distribution of states in the conduction band is revealed by the variation in power factor.