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H. Yamauchi, H. Akamatsu and T. Fujita, “An Asymtotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI’s,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 4, 1995, pp. 423-431. doi:10.1109/4.375962

has been cited by the following article:

• TITLE: Fast CR-SRAM Using New Charge-Recycling Scheme

  AUTHORS: Leilei Li, Xin Chen, Xu Wang

  KEYWORDS: SRAM; Lower-Power; Charge-Recycling

  JOURNAL NAME: Engineering, Vol.4 No.8, August 31, 2012

  ABSTRACT: In this paper, a CR-SRAM using new charge recycling scheme is described, novel bit-line pre-charge voltage distribution is proposed. The SRAM pre-charge voltage level is designed by logarithm instead of linear. The new design leads to improvement in speed compared to the original CR-SRAM. Simulation results show that the new CR-SRAM using novel pre-charge voltage distribution scheme reduced the write access time by 34% with 9% power dissipation penalty.