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J.-P. Raskin, G. Pailloncy, D. Lederer, F. Danneville, G. Dambrine, S. Decoutere, A. Mercha and B. Parvais, “High-Frequency Noise Performance of 60-nm Gate-Length FinFETs,” IEEE Transactions on Electron Devices, Vol. 55, No. 10, 2008, pp. 2718-2727. doi:10.1109/TED.2008.2003097

has been cited by the following article:

• TITLE: Design Consideration in the Development of Multi-Fin FETs for RF Applications

  AUTHORS: Peijie Feng, Prasanta Ghosh

  KEYWORDS: FinFET; Analog; RF; Source/Drain Extension Region Engineering; Simulation; Multi-Fin FET

  JOURNAL NAME: World Journal of Nano Science and Engineering, Vol.2 No.2, June 22, 2012

  ABSTRACT: In this paper, we propose multi-fin FET design techniques targeted for RF applications. Overlap and underlap design configuration in a base FinFET are compared first and then multi-fin device (consisting of transistor unit up to 50) is studied to develop design limitations and to evaluate their effects on the device performance. We have also investigated the impact of the number of fins (up to 50) in multi-fin structure and resulting RF parameters. Our results show that as the number of fin increases, underlap design compromises RF performance and short channel effects. The results provide technical understanding that is necessary to realize new opportunities for RF and analog mixed-signal design with nanoscale FinFETs.