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R. Wang, K. Li, J. Zhang and B. Nie, “A High Speed High Resolution Latch Comparator For-Pipeline ADC,” IEEE International Workshop on Anti-counterfeiting, Security, Identification, Xiamen, 16-18 April 2007, pp. 28-31.

has been cited by the following article:

• TITLE: Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

  AUTHORS: Shubhara Yewale, Radheshyam Gamad

  KEYWORDS: CMOS Comparato; Low Power; High Speed; Sigma-Delta ADC and Cadence

  JOURNAL NAME: Wireless Engineering and Technology, Vol.3 No.2, April 28, 2012

  ABSTRACT: This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.