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R. P. McEvoy, F. M. Crowe, C. C. Murphy and W. P. Marnane, “Optimisation of the SHA-2 Family of Hash Functions on FPGAs,” IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI 06), IEEE Computer Society, Washington DC, 2006, pp. 317-322.

has been cited by the following article:

• TITLE: Hardware Performance Evaluation of SHA-3 Candidate Algorithms

  AUTHORS: Yaser Jararweh, Lo’ai Tawalbeh, Hala Tawalbeh, Abidalrahman Moh’d

  KEYWORDS: Information Security; Secure Hash Algorithm (SHA); Hardware Performance; FPGA

  JOURNAL NAME: Journal of Information Security, Vol.3 No.2, April 26, 2012

  ABSTRACT: Secure Hashing Algorithms (SHA) showed a significant importance in today’s information security applications. The National Institute of Standards and Technology (NIST), held a competition of three rounds to replace SHA1 and SHA2 with the new SHA-3, to ensure long term robustness of hash functions. In this paper, we present a comprehensive hardware evaluation for the final round SHA-3 candidates. The main goal of providing the hardware evaluation is to: find the best algorithm among them that will satisfy the new hashing algorithm standards defined by the NIST. This is based on a comparison made between each of the finalists in terms of security level, throughput, clock frequancey, area, power consumption, and the cost. We expect that the achived results of the comparisons will contribute in choosing the next hashing algorithm (SHA-3) that will support the security requirements of applications in todays ubiquitous and pervasive information infrastructure.