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D. G. Mavis and P. H. Eaton, “SEU and SET Mitigation Techniques for FPGA Circuit and Configuration Bit Storage Design,” Proceedings of Military and Aerospace Applications of Programmable Devices and Technologies Confenerce, Laurel, 10-12 September 2000, pp. 1-15.

has been cited by the following article:

• TITLE: Transient and Permanent Fault Injection in VHDL Description of Digital Circuits

  AUTHORS: Parag K. Lala

  KEYWORDS: On-Line Fault Detection; VHDL; Transient Faults; Fault Injection; LFSR

  JOURNAL NAME: Circuits and Systems, Vol.3 No.2, April 19, 2012

  ABSTRACT: The ability to evaluate the testability of digital circuits before they are actually implemented is critical for designing highly reliable systems. This feature enables designers to verify the fault detection capability of online as well as offline testable digital circuits for both permanent and transient faults, during the design stage of the circuits. This paper presents a technique for transient and permanent fault injection at the VHDL level description of both combinational and sequential digital circuits. Access to all VHDL blocks a system is straight forward using a specially designed single fault injection block. This capability of inserting transient and permanent faults should help in evaluating the testability of a digital system before it is actually implemented.