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L. Cadix, C. Bermond, C. Fuchs, A. Farcy, P. Leduc, L. DiCioccio, M. Assous, M. Rousseau, F. Lorut, L. L. Chapelon, B. Flechet, N. Sillon and P. Ancey, “RF Characterization and Modelling of High Density Through Silicon Vias for 3D Chip Stacking,” Microelectronic Engineering, Vol. 87, No. 3, 2010, pp. 491-495. doi:10.1016/j.mee.2009.08.026

has been cited by the following article:

• TITLE: Analytical and Numerical Model Confrontation for Transfer Impedance Extraction in Three-Dimensional Radio Frequency Circuits

  AUTHORS: Olivier Valorge, Fengyuan Sun, Jean-Etienne Lorival, Mohamed Abouelatta-Ebrahim, Francis Calmon, Christian Gontrand

  KEYWORDS: Through Silicon Via (TSV); Green’s Function; Transmission Line Model; Radio Frequency (RF); Transfer Impedance Extraction

  JOURNAL NAME: Circuits and Systems, Vol.3 No.2, April 19, 2012

  ABSTRACT: 3D chip stacking is considered known to overcome conventional 2D-IC issues, using through silicon vias to ensure vertical signal transmission. From any point source, embedded or not, we calculate the impedance spread out; our ultimate goal will to study substrate noise via impedance field method. For this, our approach is twofold: a compact Green function or a Transmission Line Model over a multi-layered substrate is derived by solving Poisson’s equation analytically. The Discrete Cosine Transform (DCT) and its variations are used for rapid evaluation. Using this technique, the substrate coupling and loss in IC’s can be analyzed. We implement our algorithm in MATLAB; it permits to extract impedances between any pair of embedded contacts. Comparisons are performed using finite element methods.