TITLE:
Electrothermal Modelling Methodology of SiC Power MOSFET for Evaluation of Failure Cases during Short-Circuit Phases
AUTHORS:
Yannick Dumollard, Jean-Marc Dienot, Emmanuel Batista, Laurent Pecastaing
KEYWORDS:
Cauer Network, Electrothermal Model, Genetic Algorithm, Junction Temperature, MOSFET, Power Circuit, Silicon Carbide (SiC), Short-Circuit, Threshold Voltage, Transconductance
JOURNAL NAME:
Journal of Electromagnetic Analysis and Applications,
Vol.18 No.1,
January
23,
2026
ABSTRACT: We present the complete methodology to propose an efficient electrothermal model of the Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), largely used in high-power operations. The detailed model describes the non-linear electro-thermal dependencies of influent parameters in this device, such as transconductance (gm), on-state resistance (RDSON), threshold voltage (VGSTH) and parasitic capacitive elements. The rigorous identification of their values for implementation into the model is based on initial empirical and experimental determinations, which are finely processed and optimized by genetic algorithm methods (NSGA). This model is combined with a Cauer’s thermal network, determined at the chip package level, to perform electrical simulations of the SiC MOSFET activity, including the temperature couplings. With comparisons of experimental and calculated features of the MOSFET chip, validations of the model have been proved both for normal activity and for the outside range of operations of the device. Because of actual challenging issues of the reliability of SiC power transistors, electrothermal models and simulations can help to prevent effects of failure cases such as short-circuit events and assist in the diagnostic monitoring of these devices under high power and switching conditions.